ruby: MI protocol: add a missing transition

[gem5.git] / src / mem / bridge.hh

diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index c5214646335448f3f865e74cc37a825bebc3e65c..6855d27222374b0544c239f9eb71baacd096c8cc 100644 (file)
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -193,7 +193,7 @@ class Bridge : public MemObject
          */
         BridgeSlavePort(const std::string& _name, Bridge& _bridge,
                         BridgeMasterPort& _masterPort, Cycles _delay,
-                        int _resp_limit, std::vector<Range<Addr> > _ranges);
+                        int _resp_limit, std::vector<AddrRange> _ranges);
 
         /**
          * Queue a response packet to be sent out later and also schedule
@@ -338,9 +338,10 @@ class Bridge : public MemObject
 
   public:
 
-    virtual MasterPort& getMasterPort(const std::string& if_name,
-                                      int idx = -1);
-    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
+    virtual BaseMasterPort& getMasterPort(const std::string& if_name,
+                                          PortID idx = InvalidPortID);
+    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
+                                        PortID idx = InvalidPortID);
 
     virtual void init();