* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Steve Reinhardt
- * Andreas Hansson
*/
/**
* @file
- * Declaration of a memory-mapped bridge that connects a master
- * and a slave through a request and response queue.
+ * Declaration of a memory-mapped bridge that connects a requestor
+ * and a responder through a request and response queue.
*/
#ifndef __MEM_BRIDGE_HH__
#include <deque>
#include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/Bridge.hh"
+#include "sim/clocked_object.hh"
/**
* A bridge is used to interface two different crossbars (or in general a
- * memory-mapped master and slave), with buffering for requests and
+ * memory-mapped requestor and responder), with buffering for requests and
* responses. The bridge has a fixed delay for packets passing through
* it and responds to a fixed set of address ranges.
*
- * The bridge comprises a slave port and a master port, that buffer
+ * The bridge comprises a response port and a request port, that buffer
* outgoing responses and requests respectively. Buffer space is
* reserved when a request arrives, also reserving response space
* before forwarding the request. If there is no space present, then
* the bridge will delay accepting the packet until space becomes
* available.
*/
-class Bridge : public MemObject
+class Bridge : public ClockedObject
{
protected:
{ }
};
- // Forward declaration to allow the slave port to have a pointer
- class BridgeMasterPort;
+ // Forward declaration to allow the response port to have a pointer
+ class BridgeRequestPort;
/**
* The port on the side that receives requests and sends
- * responses. The slave port has a set of address ranges that it
- * is responsible for. The slave port also has a buffer for the
+ * responses. The response port has a set of address ranges that it
+ * is responsible for. The response port also has a buffer for the
* responses not yet sent.
*/
- class BridgeSlavePort : public SlavePort
+ class BridgeResponsePort : public ResponsePort
{
private:
Bridge& bridge;
/**
- * Master port on the other side of the bridge.
+ * Request port on the other side of the bridge.
*/
- BridgeMasterPort& masterPort;
+ BridgeRequestPort& memSidePort;
/** Minimum request delay though this bridge. */
const Cycles delay;
public:
/**
- * Constructor for the BridgeSlavePort.
+ * Constructor for the BridgeResponsePort.
*
* @param _name the port name including the owner
* @param _bridge the structural owner
- * @param _masterPort the master port on the other side of the bridge
+ * @param _memSidePort the request port on the other
+ * side of the bridge
* @param _delay the delay in cycles from receiving to sending
* @param _resp_limit the size of the response queue
* @param _ranges a number of address ranges to forward
*/
- BridgeSlavePort(const std::string& _name, Bridge& _bridge,
- BridgeMasterPort& _masterPort, Cycles _delay,
+ BridgeResponsePort(const std::string& _name, Bridge& _bridge,
+ BridgeRequestPort& _memSidePort, Cycles _delay,
int _resp_limit, std::vector<AddrRange> _ranges);
/**
/**
* Port on the side that forwards requests and receives
- * responses. The master port has a buffer for the requests not
+ * responses. The request port has a buffer for the requests not
* yet sent.
*/
- class BridgeMasterPort : public MasterPort
+ class BridgeRequestPort : public RequestPort
{
private:
Bridge& bridge;
/**
- * The slave port on the other side of the bridge.
+ * The response port on the other side of the bridge.
*/
- BridgeSlavePort& slavePort;
+ BridgeResponsePort& cpuSidePort;
/** Minimum delay though this bridge. */
const Cycles delay;
public:
/**
- * Constructor for the BridgeMasterPort.
+ * Constructor for the BridgeRequestPort.
*
* @param _name the port name including the owner
* @param _bridge the structural owner
- * @param _slavePort the slave port on the other side of the bridge
+ * @param _cpuSidePort the response port on the other side of
+ * the bridge
* @param _delay the delay in cycles from receiving to sending
* @param _req_limit the size of the request queue
*/
- BridgeMasterPort(const std::string& _name, Bridge& _bridge,
- BridgeSlavePort& _slavePort, Cycles _delay,
+ BridgeRequestPort(const std::string& _name, Bridge& _bridge,
+ BridgeResponsePort& _cpuSidePort, Cycles _delay,
int _req_limit);
/**
*
* @return true if we find a match
*/
- bool checkFunctional(PacketPtr pkt);
+ bool trySatisfyFunctional(PacketPtr pkt);
protected:
void recvReqRetry();
};
- /** Slave port of the bridge. */
- BridgeSlavePort slavePort;
+ /** Response port of the bridge. */
+ BridgeResponsePort cpuSidePort;
- /** Master port of the bridge. */
- BridgeMasterPort masterPort;
+ /** Request port of the bridge. */
+ BridgeRequestPort memSidePort;
public:
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
- virtual void init();
+ void init() override;
typedef BridgeParams Params;
- Bridge(Params *p);
+ Bridge(const Params &p);
};
#endif //__MEM_BRIDGE_HH__