Configs: Add support for the InOrder CPU model

[gem5.git] / src / mem / bus.hh

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 0c594c4633eab4cef18ecd70635a3ebf6ae2545a..74901d6268dac9a9c69823e15e605ec58b0e31ff 100644 (file)
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -50,6 +50,7 @@
 #include "mem/port.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
+#include "params/Bus.hh"
 
 class Bus : public MemObject
 {
@@ -130,13 +131,15 @@ class Bus : public MemObject
       public:
         BusFreeEvent(Bus * _bus);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     /** a globally unique id for this bus. */
     int busId;
     /** the clock speed for the bus */
     int clock;
+    /** cycles of overhead per transaction */
+    int headerCycles;
     /** the width of the bus in bytes */
     int width;
     /** the next tick at which the bus will be idle */
@@ -242,8 +245,15 @@ class Bus : public MemObject
      */
     void addressRanges(AddrRangeList &resp, bool &snoop, int id);
 
-    /** Occupy the bus with transmitting the packet pkt */
-    void occupyBus(PacketPtr pkt);
+    /** Calculate the timing parameters for the packet.  Updates the
+     * firstWordTime and finishTime fields of the packet object.
+     * Returns the tick at which the packet header is completed (which
+     * will be all that is sent if the target rejects the packet).
+     */
+    Tick calcPacketTiming(PacketPtr pkt);
+
+    /** Occupy the bus until until */
+    void occupyBus(Tick until);
 
     /** Ask everyone on the bus what their size is
      * @param id id of the busport that made the request
@@ -361,19 +371,21 @@ class Bus : public MemObject
 
     unsigned int drain(Event *de);
 
-    Bus(const std::string &n, int bus_id, int _clock, int _width,
-        bool responder_set, int dflt_blk_size)
-        : MemObject(n), busId(bus_id), clock(_clock), width(_width),
-          tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
-          maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
-          responderSet(responder_set), defaultBlockSize(dflt_blk_size),
+    Bus(const BusParams *p)
+        : MemObject(p), busId(p->bus_id), clock(p->clock),
+          headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
+          drainEvent(NULL), busIdle(this), inRetry(false), maxId(0),
+          defaultPort(NULL), funcPort(NULL), funcPortId(-4),
+          responderSet(p->responder_set), defaultBlockSize(p->block_size),
           cachedBlockSize(0), cachedBlockSizeValid(false)
     {
-        //Both the width and clock period must be positive
+        //width, clock period, and header cycles must be positive
         if (width <= 0)
             fatal("Bus width must be positive\n");
         if (clock <= 0)
             fatal("Bus clock period must be positive\n");
+        if (headerCycles <= 0)
+            fatal("Number of header cycles must be positive\n");
         clearBusCache();
         clearPortCache();
     }