#define __MEM_BUS_HH__
#include <string>
+#include <set>
#include <list>
-#include <inttypes.h>
-#include "base/range.hh"
#include "base/hashmap.hh"
+#include "base/range.hh"
#include "base/range_map.hh"
+#include "base/types.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/request.hh"
+#include "params/Bus.hh"
#include "sim/eventq.hh"
class Bus : public MemObject
// Ask the bus to ask everyone on the bus what their block size is and
// take the max of it. This might need to be changed a bit if we ever
// support multiple block sizes.
- virtual int deviceBlockSize()
+ virtual unsigned deviceBlockSize() const
{ return bus->findBlockSize(id); }
};
public:
BusFreeEvent(Bus * _bus);
void process();
- const char *description();
+ const char *description() const;
};
/** a globally unique id for this bus. */
int busId;
/** the clock speed for the bus */
int clock;
+ /** cycles of overhead per transaction */
+ int headerCycles;
/** the width of the bus in bytes */
int width;
/** the next tick at which the bus will be idle */
// Checks the cache and returns the id of the port that has the requested
// address within its range
inline int checkPortCache(Addr addr) {
- if (portCache[0].valid) {
- if (addr >= portCache[0].start && addr < portCache[0].end) {
- return portCache[0].id;
- } else if (portCache[1].valid) {
- if (addr >= portCache[1].start && addr < portCache[1].end) {
- return portCache[1].id;
- } else if (portCache[2].valid && addr >= portCache[2].start &&
- addr < portCache[2].end) {
- return portCache[2].id;
- }
- }
+ if (portCache[0].valid && addr >= portCache[0].start &&
+ addr < portCache[0].end) {
+ return portCache[0].id;
+ }
+ if (portCache[1].valid && addr >= portCache[1].start &&
+ addr < portCache[1].end) {
+ return portCache[1].id;
+ }
+ if (portCache[2].valid && addr >= portCache[2].start &&
+ addr < portCache[2].end) {
+ return portCache[2].id;
}
return -1;
*/
void addressRanges(AddrRangeList &resp, bool &snoop, int id);
- /** Occupy the bus with transmitting the packet pkt */
- void occupyBus(PacketPtr pkt);
+ /** Calculate the timing parameters for the packet. Updates the
+ * firstWordTime and finishTime fields of the packet object.
+ * Returns the tick at which the packet header is completed (which
+ * will be all that is sent if the target rejects the packet).
+ */
+ Tick calcPacketTiming(PacketPtr pkt);
+
+ /** Occupy the bus until until */
+ void occupyBus(Tick until);
/** Ask everyone on the bus what their size is
* @param id id of the busport that made the request
* @return the max of all the sizes
*/
- int findBlockSize(int id);
+ unsigned findBlockSize(int id);
BusFreeEvent busIdle;
bool inRetry;
+ std::set<int> inRecvStatusChange;
/** max number of bus ids we've handed out so far */
short maxId;
/** Has the user specified their own default responder? */
bool responderSet;
- int defaultBlockSize;
- int cachedBlockSize;
+ unsigned defaultBlockSize;
+ unsigned cachedBlockSize;
bool cachedBlockSizeValid;
// Cache for the peer port interfaces
// Checks the peer port interfaces cache for the port id and returns
// a pointer to the matching port
inline BusPort* checkBusCache(short id) {
- if (busCache[0].valid) {
- if (id == busCache[0].id) {
- return busCache[0].port;
- if (busCache[1].valid) {
- if (id == busCache[1].id) {
- return busCache[1].port;
- if (busCache[2].valid && id == busCache[2].id)
- return busCache[2].port;
- }
- }
- }
+ if (busCache[0].valid && id == busCache[0].id) {
+ return busCache[0].port;
+ }
+ if (busCache[1].valid && id == busCache[1].id) {
+ return busCache[1].port;
+ }
+ if (busCache[2].valid && id == busCache[2].id) {
+ return busCache[2].port;
}
return NULL;
// Invalidates the cache. Needs to be called in constructor.
inline void clearBusCache() {
- // memset(busCache, 0, 3 * sizeof(BusCache));
busCache[2].valid = false;
busCache[1].valid = false;
busCache[0].valid = false;
unsigned int drain(Event *de);
- Bus(const std::string &n, int bus_id, int _clock, int _width,
- bool responder_set, int dflt_blk_size)
- : MemObject(n), busId(bus_id), clock(_clock), width(_width),
- tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
- maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
- responderSet(responder_set), defaultBlockSize(dflt_blk_size),
+ Bus(const BusParams *p)
+ : MemObject(p), busId(p->bus_id), clock(p->clock),
+ headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
+ drainEvent(NULL), busIdle(this), inRetry(false), maxId(0),
+ defaultPort(NULL), funcPort(NULL), funcPortId(-4),
+ responderSet(p->responder_set), defaultBlockSize(p->block_size),
cachedBlockSize(0), cachedBlockSizeValid(false)
{
- //Both the width and clock period must be positive
+ //width, clock period, and header cycles must be positive
if (width <= 0)
fatal("Bus width must be positive\n");
if (clock <= 0)
fatal("Bus clock period must be positive\n");
+ if (headerCycles <= 0)
+ fatal("Number of header cycles must be positive\n");
clearBusCache();
clearPortCache();
}
projects / gem5.git / blobdiff