Port: Make getAddrRanges const

[gem5.git] / src / mem / cache / BaseCache.py

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index adc48a461aeeefa0577af2d1a4f74d6c519feaf7..83b3c70c2f8cff29c80e1719467da1d056046909 100644 (file)
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -60,5 +60,5 @@ class BaseCache(MemObject):
     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
     cpu_side = SlavePort("Port on side closer to CPU")
     mem_side = MasterPort("Port on side closer to MEM")
-    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")