Port: Make getAddrRanges const

[gem5.git] / src / mem / cache / BaseCache.py

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index e9e60859f514c5fe9723e62ad690862780f8514c..83b3c70c2f8cff29c80e1719467da1d056046909 100644 (file)
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from m5.proxy import Self
+from m5.proxy import *
 from MemObject import MemObject
 from Prefetcher import BasePrefetcher
 
@@ -44,7 +44,6 @@ class BaseCache(MemObject):
     prioritizeRequests = Param.Bool(False,
         "always service demand misses first")
     repl = Param.Repl(NULL, "replacement policy")
-    num_cpus =  Param.Int(1, "number of cpus sharing this cache")
     size = Param.MemorySize("capacity in bytes")
     forward_snoops = Param.Bool(True,
         "forward snoops from mem side to cpu side")
@@ -59,6 +58,7 @@ class BaseCache(MemObject):
     prefetch_on_access = Param.Bool(False,
          "notify the hardware prefetcher on every access (not just misses)")
     prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
-    cpu_side = Port("Port on side closer to CPU")
-    mem_side = Port("Port on side closer to MEM")
-    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+    cpu_side = SlavePort("Port on side closer to CPU")
+    mem_side = MasterPort("Port on side closer to MEM")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
+    system = Param.System(Parent.any, "System we belong to")