+# Copyright (c) 2012-2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Authors: Nathan Binkert
from m5.params import *
-from m5.proxy import Self
+from m5.proxy import *
from MemObject import MemObject
-
-class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
+from Prefetcher import BasePrefetcher
+from Tags import *
class BaseCache(MemObject):
type = 'BaseCache'
- adaptive_compression = Param.Bool(False,
- "Use an adaptive compression scheme")
+ cxx_header = "mem/cache/base.hh"
assoc = Param.Int("associativity")
- block_size = Param.Int("block size in bytes")
- latency = Param.Latency("Latency")
- compressed_bus = Param.Bool(False,
- "This cache connects to a compressed memory")
- compression_latency = Param.Latency('0ns',
- "Latency in cycles of compression algorithm")
- hash_delay = Param.Int(1, "time in cycles of hash access")
- lifo = Param.Bool(False,
- "whether this NIC partition should use LIFO repl. policy")
+ hit_latency = Param.Cycles("The hit latency for this cache")
+ response_latency = Param.Cycles(
+ "Additional cache latency for the return path to core on a miss");
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
- prioritizeRequests = Param.Bool(False,
- "always service demand misses first")
- protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
- repl = Param.Repl(NULL, "replacement policy")
size = Param.MemorySize("capacity in bytes")
- split = Param.Bool(False, "whether or not this cache is split")
- split_size = Param.Int(0,
- "How many ways of the cache belong to CPU/LRU partition")
- store_compressed = Param.Bool(False,
- "Store compressed data in the cache")
- subblock_size = Param.Int(0,
- "Size of subblock in IIC used for compression")
+ forward_snoops = Param.Bool(True,
+ "forward snoops from mem side to cpu side")
+ is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
- trace_addr = Param.Addr(0, "address to trace")
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
- prefetch_miss = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Miss stream")
- prefetch_access = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Access stream")
- prefetcher_size = Param.Int(100,
- "Number of entries in the harware prefetch queue")
- prefetch_past_page = Param.Bool(False,
- "Allow prefetches to cross virtual page boundaries")
- prefetch_serial_squash = Param.Bool(False,
- "Squash prefetches with a later time on a subsequent miss")
- prefetch_degree = Param.Int(1,
- "Degree of the prefetch depth")
- prefetch_latency = Param.Latency(10 * Self.latency,
- "Latency of the prefetcher")
- prefetch_policy = Param.Prefetch('none',
- "Type of prefetcher to use")
- prefetch_cache_check_push = Param.Bool(True,
- "Check if in cash on push or pop of prefetch queue")
- prefetch_use_cpu_id = Param.Bool(True,
- "Use the CPU ID to seperate calculations of prefetches")
- prefetch_data_accesses_only = Param.Bool(False,
- "Only prefetch on data not on instruction accesses")
- cpu_side = Port("Port on side closer to CPU")
- mem_side = Port("Port on side closer to MEM")
+ prefetch_on_access = Param.Bool(False,
+ "notify the hardware prefetcher on every access (not just misses)")
+ prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
+ cpu_side = SlavePort("Port on side closer to CPU")
+ mem_side = MasterPort("Port on side closer to MEM")
+ addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
+ system = Param.System(Parent.any, "System we belong to")
+ sequential_access = Param.Bool(False,
+ "Whether to access tags and data sequentially")
+ tags = Param.BaseTags(LRU(), "Tag Store for LRU caches")
projects / gem5.git / blobdiff