mem: write streaming support via WriteInvalidate promotion

[gem5.git] / src / mem / cache / BaseCache.py

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 6fe73a9c22e93a3747cd747b3f757f655c1d010a..9ffe399817e5e99e4ea822a7b5b9d6026f2ed8fa 100644 (file)
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -42,30 +42,23 @@ from m5.params import *
 from m5.proxy import *
 from MemObject import MemObject
 from Prefetcher import BasePrefetcher
-
+from Tags import *
 
 class BaseCache(MemObject):
     type = 'BaseCache'
+    cxx_header = "mem/cache/base.hh"
     assoc = Param.Int("associativity")
-    block_size = Param.Int("block size in bytes")
     hit_latency = Param.Cycles("The hit latency for this cache")
     response_latency = Param.Cycles(
             "Additional cache latency for the return path to core on a miss");
-    hash_delay = Param.Cycles(1, "time in cycles of hash access")
     max_miss_count = Param.Counter(0,
         "number of misses to handle before calling exit")
     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
-    prioritizeRequests = Param.Bool(False,
-        "always service demand misses first")
-    repl = Param.Repl(NULL, "replacement policy")
     size = Param.MemorySize("capacity in bytes")
     forward_snoops = Param.Bool(True,
         "forward snoops from mem side to cpu side")
     is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
-    subblock_size = Param.Int(0,
-        "Size of subblock in IIC used for compression")
     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
-    trace_addr = Param.Addr(0, "address to trace")
     two_queue = Param.Bool(False,
         "whether the lifo should have two queue replacement")
     write_buffers = Param.Int(8, "number of write buffers")
@@ -76,3 +69,6 @@ class BaseCache(MemObject):
     mem_side = MasterPort("Port on side closer to MEM")
     addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port")
     system = Param.System(Parent.any, "System we belong to")
+    sequential_access = Param.Bool(False,
+        "Whether to access tags and data sequentially")
+    tags = Param.BaseTags(LRU(), "Tag Store for LRU caches")