mem-cache: Use shouldAllocate() instead of CPack's decompress()

[gem5.git] / src / mem / cache / Cache.py

diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 0a590c2ca5d4a0b9aeeee2b2cc7c2112a6aa5b4e..7a28136b5de1443e0f1abb8e119f04636ad422be 100644 (file)
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,12 +43,12 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Compressors import BaseCacheCompressor
 from m5.objects.Prefetcher import BasePrefetcher
 from m5.objects.ReplacementPolicies import *
 from m5.objects.Tags import *
 
-
 # Enum for cache clusivity, currently mostly inclusive or mostly
 # exclusive.
 class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
@@ -72,7 +72,7 @@ class WriteAllocator(SimObject):
     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
 
 
-class BaseCache(MemObject):
+class BaseCache(ClockedObject):
     type = 'BaseCache'
     abstract = True
     cxx_header = "mem/cache/base.hh"
@@ -105,6 +105,8 @@ class BaseCache(MemObject):
     replacement_policy = Param.BaseReplacementPolicy(LRURP(),
         "Replacement policy")
 
+    compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
+
     sequential_access = Param.Bool(False,
         "Whether to access tags and data sequentially")