mem-cache: Virtualize block print

[gem5.git] / src / mem / cache / SConscript

diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index d5899b6232302c7c2915fec9ec213491c1964b4a..24eea960e9bff2e4b6a9c0c5ea377d5ecbc5851f 100644 (file)
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,14 +30,28 @@
 
 Import('*')
 
-SimObject('BaseCache.py')
+SimObject('Cache.py')
 
-Source('base_cache.cc')
+Source('base.cc')
+Source('blk.cc')
 Source('cache.cc')
-Source('cache_blk.cc')
-Source('cache_builder.cc')
+Source('mshr.cc')
+Source('mshr_queue.cc')
+Source('noncoherent_cache.cc')
+Source('sector_blk.cc')
+Source('write_queue.cc')
+Source('write_queue_entry.cc')
+
+DebugFlag('Cache')
+DebugFlag('CachePort')
+DebugFlag('CacheRepl')
+DebugFlag('CacheTags')
+DebugFlag('CacheVerbose')
+DebugFlag('HWPrefetch')
+
+# CacheTags is so outrageously verbose, printing the cache's entire tag
+# array on each timing access, that you should probably have to ask for
+# it explicitly even above and beyond CacheAll.
+CompoundFlag('CacheAll', ['Cache', 'CachePort', 'CacheRepl', 'CacheVerbose',
+                          'HWPrefetch'])
 
-TraceFlag('Cache')
-TraceFlag('CachePort')
-TraceFlag('CacheRepl')
-TraceFlag('HWPrefetch')