MEM: Separate queries for snooping and address ranges

[gem5.git] / src / mem / cache / base.cc

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 95637553014bbeb488ff4558d8e22f96dfd39928..278329152a9f7053d27fbe2bce4fb1f816b410e0 100644 (file)
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -35,17 +35,17 @@
 
 #include "cpu/base.hh"
 #include "cpu/smt.hh"
+#include "debug/Cache.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/mshr.hh"
 
 using namespace std;
 
 BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
-                                const std::string &_label,
-                                std::vector<Range<Addr> > filter_ranges)
+                                const std::string &_label)
     : SimpleTimingPort(_name, _cache), cache(_cache),
       label(_label), otherPort(NULL),
-      blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
+      blocked(false), mustSendRetry(false)
 {
 }
 
@@ -58,19 +58,21 @@ BaseCache::BaseCache(const Params *p)
       blkSize(p->block_size),
       hitLatency(p->latency),
       numTarget(p->tgts_per_mshr),
+      forwardSnoops(p->forward_snoops),
+      isTopLevel(p->is_top_level),
       blocked(0),
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
-      drainEvent(NULL)
+      drainEvent(NULL),
+      addrRange(p->addr_range),
+      _numCpus(p->num_cpus)
 {
 }
 
 void
-BaseCache::CachePort::recvStatusChange(Port::Status status)
+BaseCache::CachePort::recvRangeChange() const
 {
-    if (status == Port::RangeChange) {
-        otherPort->sendStatusChange(Port::RangeChange);
-    }
+    otherPort->sendRangeChange();
 }
 
 
@@ -84,8 +86,8 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt)
 }
 
 
-int
-BaseCache::CachePort::deviceBlockSize()
+unsigned
+BaseCache::CachePort::deviceBlockSize() const
 {
     return cache->getBlockSize();
 }
@@ -122,7 +124,7 @@ BaseCache::CachePort::clearBlocked()
         mustSendRetry = false;
         SendRetryEvent *ev = new SendRetryEvent(this, true);
         // @TODO: need to find a better time (next bus cycle?)
-        schedule(ev, curTick + 1);
+        cache->schedule(ev, curTick() + 1);
     }
 }
 
@@ -132,7 +134,7 @@ BaseCache::init()
 {
     if (!cpuSidePort || !memSidePort)
         panic("Cache not hooked up on both sides\n");
-    cpuSidePort->sendStatusChange(Port::RangeChange);
+    cpuSidePort->sendRangeChange();
 }
 
 
@@ -147,7 +149,11 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         hits[access_idx]
-            .init(maxThreadsPerCPU)
+#if FULL_SYSTEM
+            .init(_numCpus + 1)
+#else
+            .init(_numCpus)
+#endif
             .name(name() + "." + cstr + "_hits")
             .desc("number of " + cstr + " hits")
             .flags(total | nozero | nonan)
@@ -184,7 +190,11 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         misses[access_idx]
-            .init(maxThreadsPerCPU)
+#if FULL_SYSTEM
+            .init(_numCpus + 1)
+#else
+            .init(_numCpus)
+#endif
             .name(name() + "." + cstr + "_misses")
             .desc("number of " + cstr + " misses")
             .flags(total | nozero | nonan)