#include <string>
#include <list>
#include <algorithm>
-#include <inttypes.h>
#include "base/misc.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
+#include "base/types.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
protected:
CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filter_ranges);
+ const std::string &_label);
virtual void recvStatusChange(Status status);
- virtual int deviceBlockSize();
+ virtual unsigned deviceBlockSize() const;
bool recvRetryCommon();
bool mustSendRetry;
- /** filter ranges */
- std::vector<Range<Addr> > filterRanges;
-
void requestBus(RequestCause cause, Tick time)
{
DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
}
/** Block size of this cache */
- const int blkSize;
+ const unsigned blkSize;
/**
* The latency of a hit in this device.
/** The number of targets for each MSHR. */
const int numTarget;
- /** Increasing order number assigned to each incoming request. */
- uint64_t order;
+ /** Do we forward snoops from mem side port through to cpu side port? */
+ bool forwardSnoops;
/**
* Bit vector of the blocking reasons for the access path.
*/
uint8_t blocked;
+ /** Increasing order number assigned to each incoming request. */
+ uint64_t order;
+
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
/** The drain event. */
Event *drainEvent;
+ /**
+ * The address range to which the cache responds on the CPU side.
+ * Normally this is all possible memory addresses. */
+ Range<Addr> addrRange;
+
public:
// Statistics
/**
*/
/** Number of hits per thread for each type of command. @sa Packet::Command */
- Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
/** Number of hits for demand accesses. */
Stats::Formula demandHits;
/** Number of hit for all accesses. */
Stats::Formula overallHits;
/** Number of misses per thread for each type of command. @sa Packet::Command */
- Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
/** Number of misses for demand accesses. */
Stats::Formula demandMisses;
/** Number of misses for all accesses. */
* Total number of cycles per thread/command spent waiting for a miss.
* Used to calculate the average miss latency.
*/
- Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
/** Total number of cycles spent waiting for demand misses. */
Stats::Formula demandMissLatency;
/** Total number of cycles spent waiting for all misses. */
Stats::Formula overallAvgMissLatency;
/** The total number of cycles blocked for each blocked cause. */
- Stats::Vector<> blocked_cycles;
+ Stats::Vector blocked_cycles;
/** The number of times this cache blocked for each blocked cause. */
- Stats::Vector<> blocked_causes;
+ Stats::Vector blocked_causes;
/** The average number of cycles blocked for each blocked cause. */
Stats::Formula avg_blocked;
/** The number of fast writes (WH64) performed. */
- Stats::Scalar<> fastWrites;
+ Stats::Scalar fastWrites;
/** The number of cache copies performed. */
- Stats::Scalar<> cacheCopies;
+ Stats::Scalar cacheCopies;
/** Number of blocks written back per thread. */
- Stats::Vector<> writebacks;
+ Stats::Vector writebacks;
/** Number of misses that hit in the MSHRs per command and thread. */
- Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
/** Demand misses that hit in the MSHRs. */
Stats::Formula demandMshrHits;
/** Total number of misses that hit in the MSHRs. */
Stats::Formula overallMshrHits;
/** Number of misses that miss in the MSHRs, per command and thread. */
- Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
/** Demand misses that miss in the MSHRs. */
Stats::Formula demandMshrMisses;
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrMisses;
/** Number of misses that miss in the MSHRs, per command and thread. */
- Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrUncacheable;
/** Total cycle latency of each MSHR miss, per command and thread. */
- Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of demand MSHR misses. */
Stats::Formula demandMshrMissLatency;
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrMissLatency;
/** Total cycle latency of each MSHR miss, per command and thread. */
- Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
+ Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrUncacheableLatency;
Stats::Formula overallAvgMshrUncacheableLatency;
/** The number of times a thread hit its MSHR cap. */
- Stats::Vector<> mshr_cap_events;
+ Stats::Vector mshr_cap_events;
/** The number of times software prefetches caused the MSHR to block. */
- Stats::Vector<> soft_prefetch_mshr_full;
+ Stats::Vector soft_prefetch_mshr_full;
- Stats::Scalar<> mshr_no_allocate_misses;
+ Stats::Scalar mshr_no_allocate_misses;
/**
* @}
* Query block size of a cache.
* @return The block size
*/
- int getBlockSize() const
+ unsigned
+ getBlockSize() const
{
return blkSize;
}
- Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); }
+ Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
+
+ const Range<Addr> &getAddrRange() const { return addrRange; }
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
{
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