* Definition of BaseCache functions.
*/
-#include "mem/cache/base_cache.hh"
-#include "cpu/smt.hh"
#include "cpu/base.hh"
+#include "cpu/smt.hh"
+#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/mshr.hh"
using namespace std;
: Port(_name), cache(_cache), isCpuSide(_isCpuSide)
{
blocked = false;
+ waitingOnRetry = false;
//Start ports at null if more than one is created we should panic
//cpuSidePort = NULL;
//memSidePort = NULL;
BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{
- cache->getAddressRanges(resp, snoop);
+ cache->getAddressRanges(resp, snoop, isCpuSide);
}
int
}
bool
-BaseCache::CachePort::recvTiming(Packet *pkt)
+BaseCache::CachePort::recvTiming(PacketPtr pkt)
{
+ if (isCpuSide
+ && !pkt->req->isUncacheable()
+ && pkt->isInvalidate()
+ && !pkt->isRead() && !pkt->isWrite()) {
+ //Upgrade or Invalidate
+ //Look into what happens if two slave caches on bus
+ DPRINTF(Cache, "%s %x ? blk_addr: %x\n", pkt->cmdString(),
+ pkt->getAddr() & (((ULL(1))<<48)-1),
+ pkt->getAddr() & ~((Addr)cache->blkSize - 1));
+
+ assert(!(pkt->flags & SATISFIED));
+ pkt->flags |= SATISFIED;
+ //Invalidates/Upgrades need no response if they get the bus
+ return true;
+ }
+
+ if (pkt->isRequest() && blocked)
+ {
+ DPRINTF(Cache,"Scheduling a retry while blocked\n");
+ mustSendRetry = true;
+ return false;
+ }
return cache->doTimingAccess(pkt, this, isCpuSide);
}
Tick
-BaseCache::CachePort::recvAtomic(Packet *pkt)
+BaseCache::CachePort::recvAtomic(PacketPtr pkt)
{
return cache->doAtomicAccess(pkt, isCpuSide);
}
void
-BaseCache::CachePort::recvFunctional(Packet *pkt)
+BaseCache::CachePort::recvFunctional(PacketPtr pkt)
{
+ //Check storage here first
+ list<PacketPtr>::iterator i = drainList.begin();
+ list<PacketPtr>::iterator end = drainList.end();
+ for (; i != end; ++i) {
+ PacketPtr target = *i;
+ // If the target contains data, and it overlaps the
+ // probed request, need to update data
+ if (target->intersect(pkt)) {
+ fixPacket(pkt, target);
+ }
+ }
cache->doFunctionalAccess(pkt, isCpuSide);
}
+void
+BaseCache::CachePort::recvRetry()
+{
+ PacketPtr pkt;
+ assert(waitingOnRetry);
+ if (!drainList.empty()) {
+ DPRINTF(CachePort, "%s attempting to send a retry for response\n", name());
+ //We have some responses to drain first
+ if (sendTiming(drainList.front())) {
+ DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name());
+ drainList.pop_front();
+ if (!drainList.empty() ||
+ !isCpuSide && cache->doMasterRequest() ||
+ isCpuSide && cache->doSlaveRequest()) {
+
+ DPRINTF(CachePort, "%s has more responses/requests\n", name());
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
+ reqCpu->schedule(curTick + 1);
+ }
+ waitingOnRetry = false;
+ }
+ }
+ else if (!isCpuSide)
+ {
+ DPRINTF(CachePort, "%s attempting to send a retry for MSHR\n", name());
+ if (!cache->doMasterRequest()) {
+ //This can happen if I am the owner of a block and see an upgrade
+ //while the block was in my WB Buffers. I just remove the
+ //wb and de-assert the masterRequest
+ waitingOnRetry = false;
+ return;
+ }
+ pkt = cache->getPacket();
+ MSHR* mshr = (MSHR*) pkt->senderState;
+ //Copy the packet, it may be modified/destroyed elsewhere
+ PacketPtr copyPkt = new Packet(*pkt);
+ copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
+ mshr->pkt = copyPkt;
+
+ bool success = sendTiming(pkt);
+ DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+ pkt->getAddr(), success ? "succesful" : "unsuccesful");
+
+ waitingOnRetry = !success;
+ if (waitingOnRetry) {
+ DPRINTF(CachePort, "%s now waiting on a retry\n", name());
+ }
+
+ cache->sendResult(pkt, mshr, success);
+
+ if (success && cache->doMasterRequest())
+ {
+ DPRINTF(CachePort, "%s has more requests\n", name());
+ //Still more to issue, rerequest in 1 cycle
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
+ reqCpu->schedule(curTick + 1);
+ }
+ }
+ else
+ {
+ assert(cache->doSlaveRequest());
+ //pkt = cache->getCoherencePacket();
+ //We save the packet, no reordering on CSHRS
+ pkt = cache->getCoherencePacket();
+ MSHR* cshr = (MSHR*)pkt->senderState;
+ bool success = sendTiming(pkt);
+ cache->sendCoherenceResult(pkt, cshr, success);
+ waitingOnRetry = !success;
+ if (success && cache->doSlaveRequest())
+ {
+ DPRINTF(CachePort, "%s has more requests\n", name());
+ //Still more to issue, rerequest in 1 cycle
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
+ reqCpu->schedule(curTick + 1);
+ }
+ }
+ if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name());
+ else DPRINTF(CachePort, "%s no longer waiting on retry\n", name());
+ return;
+}
void
BaseCache::CachePort::setBlocked()
{
+ assert(!blocked);
+ DPRINTF(Cache, "Cache Blocking\n");
blocked = true;
+ //Clear the retry flag
+ mustSendRetry = false;
}
void
BaseCache::CachePort::clearBlocked()
{
+ assert(blocked);
+ DPRINTF(Cache, "Cache Unblocking\n");
blocked = false;
+ if (mustSendRetry)
+ {
+ DPRINTF(Cache, "Cache Sending Retry\n");
+ mustSendRetry = false;
+ sendRetry();
+ }
}
BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
pkt = NULL;
}
-BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt)
: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
{
this->setFlags(AutoDelete);
{
if (!pkt)
{
- if (!cachePort->isCpuSide)
+ if (cachePort->waitingOnRetry) return;
+ //We have some responses to drain first
+ if (!cachePort->drainList.empty()) {
+ DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name());
+ if (cachePort->sendTiming(cachePort->drainList.front())) {
+ DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name());
+ cachePort->drainList.pop_front();
+ if (!cachePort->drainList.empty() ||
+ !cachePort->isCpuSide && cachePort->cache->doMasterRequest() ||
+ cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) {
+
+ DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name());
+ this->schedule(curTick + 1);
+ }
+ }
+ else {
+ cachePort->waitingOnRetry = true;
+ DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
+ }
+ }
+ else if (!cachePort->isCpuSide)
+ { //MSHR
+ DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name());
+ if (!cachePort->cache->doMasterRequest()) {
+ //This can happen if I am the owner of a block and see an upgrade
+ //while the block was in my WB Buffers. I just remove the
+ //wb and de-assert the masterRequest
+ return;
+ }
+
pkt = cachePort->cache->getPacket();
- //Else get coherence req
+ MSHR* mshr = (MSHR*) pkt->senderState;
+ //Copy the packet, it may be modified/destroyed elsewhere
+ PacketPtr copyPkt = new Packet(*pkt);
+ copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>());
+ mshr->pkt = copyPkt;
+
+ bool success = cachePort->sendTiming(pkt);
+ DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+ pkt->getAddr(), success ? "succesful" : "unsuccesful");
+
+ cachePort->waitingOnRetry = !success;
+ if (cachePort->waitingOnRetry) {
+ DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
+ }
+
+ cachePort->cache->sendResult(pkt, mshr, success);
+ if (success && cachePort->cache->doMasterRequest())
+ {
+ DPRINTF(CachePort, "%s still more MSHR requests to send\n",
+ cachePort->name());
+ //Still more to issue, rerequest in 1 cycle
+ pkt = NULL;
+ this->schedule(curTick+1);
+ }
+ }
+ else
+ {
+ //CSHR
+ assert(cachePort->cache->doSlaveRequest());
+ pkt = cachePort->cache->getCoherencePacket();
+ MSHR* cshr = (MSHR*) pkt->senderState;
+ bool success = cachePort->sendTiming(pkt);
+ cachePort->cache->sendCoherenceResult(pkt, cshr, success);
+ cachePort->waitingOnRetry = !success;
+ if (cachePort->waitingOnRetry)
+ DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name());
+ if (success && cachePort->cache->doSlaveRequest())
+ {
+ DPRINTF(CachePort, "%s still more CSHR requests to send\n",
+ cachePort->name());
+ //Still more to issue, rerequest in 1 cycle
+ pkt = NULL;
+ this->schedule(curTick+1);
+ }
+ }
+ return;
+ }
+ //Response
+ //Know the packet to send
+ if (pkt->flags & NACKED_LINE)
+ pkt->result = Packet::Nacked;
+ else
+ pkt->result = Packet::Success;
+ pkt->makeTimingResponse();
+ DPRINTF(CachePort, "%s attempting to send a response\n", cachePort->name());
+ if (!cachePort->drainList.empty() || cachePort->waitingOnRetry) {
+ //Already have a list, just append
+ cachePort->drainList.push_back(pkt);
+ DPRINTF(CachePort, "%s appending response onto drain list\n", cachePort->name());
+ }
+ else if (!cachePort->sendTiming(pkt)) {
+ //It failed, save it to list of drain events
+ DPRINTF(CachePort, "%s now waiting for a retry\n", cachePort->name());
+ cachePort->drainList.push_back(pkt);
+ cachePort->waitingOnRetry = true;
}
- cachePort->sendTiming(pkt);
}
const char *
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
- if (if_name == "functional")
+ else if (if_name == "functional")
+ {
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ return cpuSidePort;
+ }
+ else if (if_name == "cpu_side")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
else panic("Port name %s unrecognized\n", if_name);
}
+void
+BaseCache::init()
+{
+ if (!cpuSidePort || !memSidePort)
+ panic("Cache not hooked up on both sides\n");
+ cpuSidePort->sendStatusChange(Port::RangeChange);
+}
+
void
BaseCache::regStats()
{
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