Get rid of unused CacheBlk << output operator.

[gem5.git] / src / mem / cache / base_cache.hh

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 2e92e77300bfdcb9284115f0b3f1d848ffbc015e..455e13d9c8f2cf441923aae6d22fe2b9efb43515 100644 (file)
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -72,6 +72,7 @@ enum RequestCause{
     Request_PF
 };
 
+class MSHR;
 /**
  * A basic cache interface. Implements some common functions for speed.
  */
@@ -111,7 +112,11 @@ class BaseCache : public MemObject
 
         bool isCpuSide;
 
+        bool waitingOnRetry;
+
         std::list<Packet *> drainList;
+
+        Packet *cshrRetry;
     };
 
     struct CacheEvent : public Event
@@ -156,7 +161,7 @@ class BaseCache : public MemObject
         if (status == Port::RangeChange){
             if (!isCpuSide) {
                 cpuSidePort->sendStatusChange(Port::RangeChange);
-                if (topLevelCache && !snoopRangesSent) {
+                if (!snoopRangesSent) {
                     snoopRangesSent = true;
                     memSidePort->sendStatusChange(Port::RangeChange);
                 }
@@ -177,7 +182,7 @@ class BaseCache : public MemObject
         fatal("No implementation");
     }
 
-    virtual void sendResult(Packet* &pkt, bool success)
+    virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success)
     {
 
         fatal("No implementation");
@@ -207,10 +212,6 @@ class BaseCache : public MemObject
 
   protected:
 
-    /** True if this cache is connected to the CPU. */
-    bool topLevelCache;
-
-
     /** Stores time the cache blocked for statistics. */
     Tick blockedCycle;
 
@@ -332,7 +333,7 @@ class BaseCache : public MemObject
      */
     BaseCache(const std::string &name, Params &params)
         : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
-          slaveRequests(0), topLevelCache(false),  blkSize(params.blkSize),
+          slaveRequests(0), blkSize(params.blkSize),
           missCount(params.maxMisses)
     {
         //Start ports at null if more than one is created we should panic
@@ -352,15 +353,6 @@ class BaseCache : public MemObject
         return blkSize;
     }
 
-    /**
-     * Returns true if this cache is connect to the CPU.
-     * @return True if this is a L1 cache.
-     */
-    bool isTopLevel()
-    {
-        return topLevelCache;
-    }
-
     /**
      * Returns true if the cache is blocked for accesses.
      */
@@ -389,11 +381,13 @@ class BaseCache : public MemObject
             blocked_causes[cause]++;
             blockedCycle = curTick;
         }
+        int old_state = blocked;
         if (!(blocked & flag)) {
             //Wasn't already blocked for this cause
             blocked |= flag;
             DPRINTF(Cache,"Blocking for cause %s\n", cause);
-            cpuSidePort->setBlocked();
+            if (!old_state)
+                cpuSidePort->setBlocked();
         }
     }
 
@@ -405,10 +399,12 @@ class BaseCache : public MemObject
     void setBlockedForSnoop(BlockedCause cause)
     {
         uint8_t flag = 1 << cause;
-        if (!(blocked & flag)) {
+        uint8_t old_state = blockedSnoop;
+        if (!(blockedSnoop & flag)) {
             //Wasn't already blocked for this cause
             blockedSnoop |= flag;
-            memSidePort->setBlocked();
+            if (!old_state)
+                memSidePort->setBlocked();
         }
     }
 
@@ -458,7 +454,7 @@ class BaseCache : public MemObject
      */
     void setMasterRequest(RequestCause cause, Tick time)
     {
-        if (!doMasterRequest())
+        if (!doMasterRequest() && !memSidePort->waitingOnRetry)
         {
             BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
             reqCpu->schedule(time);
@@ -520,6 +516,10 @@ class BaseCache : public MemObject
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+        else {
+            if (pkt->cmd == Packet::Writeback) delete pkt->req;
+            delete pkt;
+        }
     }
 
     /**
@@ -536,6 +536,10 @@ class BaseCache : public MemObject
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+        else {
+            if (pkt->cmd == Packet::Writeback) delete pkt->req;
+            delete pkt;
+        }
     }
 
     /**
@@ -544,8 +548,6 @@ class BaseCache : public MemObject
      */
     void respondToSnoop(Packet *pkt, Tick time)
     {
-//        assert("Implement\n" && 0);
-//     mi->respond(pkt,curTick + hitLatency);
         assert (pkt->needsResponse());
         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
         reqMem->schedule(time);
@@ -568,15 +570,7 @@ class BaseCache : public MemObject
         {
             //This is where snoops get updated
             AddrRangeList dummy;
-            if (!topLevelCache)
-            {
-                cpuSidePort->getPeerAddressRanges(dummy, snoop);
-            }
-            else
-            {
-                snoop.push_back(RangeSize(0,-1));
-            }
-
+            cpuSidePort->getPeerAddressRanges(dummy, snoop);
             return;
         }
     }