/*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* Definitions of a simple cache block class.
*/
-#ifndef __CACHE_BLK_HH__
-#define __CACHE_BLK_HH__
+#ifndef __MEM_CACHE_BLK_HH__
+#define __MEM_CACHE_BLK_HH__
+#include <cassert>
+#include <cstdint>
+#include <iosfwd>
#include <list>
+#include <string>
#include "base/printable.hh"
+#include "base/types.hh"
+#include "mem/cache/replacement_policies/base.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
-#include "sim/core.hh" // for Tick
/**
* Cache block status bit assignments
*/
-enum CacheBlkStatusBits {
+enum CacheBlkStatusBits : unsigned {
/** valid, readable */
BlkValid = 0x01,
/** write permission */
BlkReadable = 0x04,
/** dirty (modified) */
BlkDirty = 0x08,
- /** block was referenced */
- BlkReferenced = 0x10,
/** block was a hardware prefetch yet unaccessed*/
BlkHWPrefetched = 0x20,
/** block holds data from the secure memory space */
BlkSecure = 0x40,
- /** can the block transition to E? (hasn't been shared with another cache)
- * used to close a timing gap when handling WriteInvalidate packets */
- BlkCanGoExclusive = 0x80
};
/**
* A Basic Cache block.
* Contains the tag, status, and a pointer to data.
*/
-class CacheBlk
+class CacheBlk : public ReplaceableEntry
{
public:
/** Task Id associated with this block */
uint32_t task_id;
- /** The address space ID of this block. */
- int asid;
/** Data block tag value. */
Addr tag;
/**
* referenced by this block.
*/
uint8_t *data;
- /** the number of bytes stored in this block. */
- int size;
/** block state: OR of CacheBlkStatusBit */
typedef unsigned State;
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick() will this block be accessable */
+ /** Which curTick() will this block be accessible */
Tick whenReady;
- /**
- * The set this block belongs to.
- * @todo Move this into subclasses when we fix CacheTags to use them.
- */
- int set;
-
- /** whether this block has been touched */
- bool isTouched;
-
/** Number of references to this block since it was brought in. */
- int refCount;
+ unsigned refCount;
/** holds the source requestor ID for this block. */
int srcMasterId;
+ /** Tick on which the block was inserted in the cache. */
Tick tickInserted;
protected:
*/
class Lock {
public:
- int contextId; // locking context
+ ContextID contextId; // locking context
Addr lowAddr; // low address of lock range
Addr highAddr; // high address of lock range
- // check for matching execution context
- bool matchesContext(Request *req)
+ // check for matching execution context, and an address that
+ // is within the lock
+ bool matches(const RequestPtr &req) const
{
Addr req_low = req->getPaddr();
Addr req_high = req_low + req->getSize() -1;
(req_low >= lowAddr) && (req_high <= highAddr);
}
- bool overlapping(Request *req)
+ // check if a request is intersecting and thus invalidating the lock
+ bool intersects(const RequestPtr &req) const
{
Addr req_low = req->getPaddr();
Addr req_high = req_low + req->getSize() - 1;
return (req_low <= highAddr) && (req_high >= lowAddr);
}
- Lock(Request *req)
+ Lock(const RequestPtr &req)
: contextId(req->contextId()),
lowAddr(req->getPaddr()),
highAddr(lowAddr + req->getSize() - 1)
std::list<Lock> lockList;
public:
-
- CacheBlk()
- : task_id(ContextSwitchTaskId::Unknown),
- asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
- set(-1), isTouched(false), refCount(0),
- srcMasterId(Request::invldMasterId),
- tickInserted(0)
- {}
-
- /**
- * Copy the state of the given block into this one.
- * @param rhs The block to copy.
- * @return a const reference to this block.
- */
- const CacheBlk& operator=(const CacheBlk& rhs)
+ CacheBlk() : data(nullptr)
{
- asid = rhs.asid;
- tag = rhs.tag;
- data = rhs.data;
- size = rhs.size;
- status = rhs.status;
- whenReady = rhs.whenReady;
- set = rhs.set;
- refCount = rhs.refCount;
- task_id = rhs.task_id;
- return *this;
+ invalidate();
}
+ CacheBlk(const CacheBlk&) = delete;
+ CacheBlk& operator=(const CacheBlk&) = delete;
+ virtual ~CacheBlk() {};
+
/**
* Checks the write permissions of this block.
* @return True if the block is writable.
/**
* Invalidate the block and clear all state.
*/
- void invalidate()
+ virtual void invalidate()
{
+ tag = MaxAddr;
+ task_id = ContextSwitchTaskId::Unknown;
status = 0;
- isTouched = false;
- clearLoadLocks();
+ whenReady = MaxTick;
+ refCount = 0;
+ srcMasterId = Request::invldMasterId;
+ tickInserted = MaxTick;
+ lockList.clear();
}
/**
return (status & BlkDirty) != 0;
}
- /**
- * Check if this block has been referenced.
- * @return True if the block has been referenced.
- */
- bool isReferenced() const
- {
- return (status & BlkReferenced) != 0;
- }
-
/**
* Check if this block was the result of a hardware prefetch, yet to
* be touched.
}
/**
- * Track the fact that a local locked was issued to the block. If
- * multiple LLs get issued from the same context we could have
- * redundant records on the list, but that's OK, as they'll all
- * get blown away at the next store.
+ * Set member variables when a block insertion occurs. Resets reference
+ * count to 1 (the insertion counts as a reference), and touch block if
+ * it hadn't been touched previously. Sets the insertion tick to the
+ * current tick. Does not make block valid.
+ *
+ * @param tag Block address tag.
+ * @param is_secure Whether the block is in secure space or not.
+ * @param src_master_ID The source requestor ID.
+ * @param task_ID The new task ID.
+ */
+ virtual void insert(const Addr tag, const bool is_secure,
+ const int src_master_ID, const uint32_t task_ID);
+
+ /**
+ * Track the fact that a local locked was issued to the
+ * block. Invalidate any previous LL to the same address.
*/
void trackLoadLocked(PacketPtr pkt)
{
assert(pkt->isLLSC());
- lockList.push_front(Lock(pkt->req));
+ auto l = lockList.begin();
+ while (l != lockList.end()) {
+ if (l->intersects(pkt->req))
+ l = lockList.erase(l);
+ else
+ ++l;
+ }
+
+ lockList.emplace_front(pkt->req);
}
/**
- * Clear the list of valid load locks. Should be called whenever
- * block is written to or invalidated.
+ * Clear the any load lock that intersect the request, and is from
+ * a different context.
*/
- void clearLoadLocks(Request *req = NULL)
+ void clearLoadLocks(const RequestPtr &req)
{
- if (!req) {
- // No request, invaldate all locks to this line
- lockList.clear();
- } else {
- // Only invalidate locks that overlap with this request
- std::list<Lock>::iterator lock_itr = lockList.begin();
- while (lock_itr != lockList.end()) {
- if (lock_itr->overlapping(req)) {
- lock_itr = lockList.erase(lock_itr);
- } else {
- ++lock_itr;
- }
+ auto l = lockList.begin();
+ while (l != lockList.end()) {
+ if (l->intersects(req) && l->contextId != req->contextId()) {
+ l = lockList.erase(l);
+ } else {
+ ++l;
}
}
}
/**
- * Pretty-print a tag, and interpret state bits to readable form
- * including mapping to a MOESI stat.
+ * Pretty-print tag, set and way, and interpret state bits to readable form
+ * including mapping to a MOESI state.
*
* @return string with basic state information
*/
- std::string print() const
+ virtual std::string print() const
{
/**
* state M O E S I
* E 1 0 1
* S 0 0 1
* I 0 0 0
+ *
+ * Note that only one cache ever has a block in Modified or
+ * Owned state, i.e., only one cache owns the block, or
+ * equivalently has the BlkDirty bit set. However, multiple
+ * caches on the same path to memory can have a block in the
+ * Exclusive state (despite the name). Exclusive means this
+ * cache has the only copy at this level of the hierarchy,
+ * i.e., there may be copies in caches above this cache (in
+ * various states), but there are no peers that have copies on
+ * this branch of the hierarchy, and no caches at or above
+ * this level on any other branch have copies either.
**/
unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
char s = '?';
default: s = 'T'; break; // @TODO add other types
}
return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
- "dirty: %d tag: %x", status, s, isValid(),
- isWritable(), isReadable(), isDirty(), tag);
+ "dirty: %d | tag: %#x set: %#x way: %#x", status, s,
+ isValid(), isWritable(), isReadable(), isDirty(), tag,
+ getSet(), getWay());
}
/**
*/
bool checkWrite(PacketPtr pkt)
{
- Request *req = pkt->req;
+ assert(pkt->isWrite());
+
+ // common case
+ if (!pkt->isLLSC() && lockList.empty())
+ return true;
+
+ const RequestPtr &req = pkt->req;
+
if (pkt->isLLSC()) {
// it's a store conditional... have to check for matching
// load locked.
bool success = false;
- for (std::list<Lock>::iterator i = lockList.begin();
- i != lockList.end(); ++i)
- {
- if (i->matchesContext(req)) {
- // it's a store conditional, and as far as the memory
- // system can tell, the requesting context's lock is
- // still valid.
+ auto l = lockList.begin();
+ while (!success && l != lockList.end()) {
+ if (l->matches(pkt->req)) {
+ // it's a store conditional, and as far as the
+ // memory system can tell, the requesting
+ // context's lock is still valid.
success = true;
- break;
+ lockList.erase(l);
+ } else {
+ ++l;
}
}
req->setExtraData(success ? 1 : 0);
+ // clear any intersected locks from other contexts (our LL
+ // should already have cleared them)
clearLoadLocks(req);
return success;
} else {
- // for *all* stores (conditional or otherwise) we have to
- // clear the list of load-locks as they're all invalid now.
+ // a normal write, if there is any lock not from this
+ // context we clear the list, thus for a private cache we
+ // never clear locks on normal writes
clearLoadLocks(req);
return true;
}
};
/**
- * Simple class to provide virtual print() method on cache blocks
- * without allocating a vtable pointer for every single cache block.
- * Just wrap the CacheBlk object in an instance of this before passing
- * to a function that requires a Printable object.
+ * Special instance of CacheBlk for use with tempBlk that deals with its
+ * block address regeneration.
+ * @sa Cache
*/
-class CacheBlkPrintWrapper : public Printable
+class TempCacheBlk final : public CacheBlk
{
- CacheBlk *blk;
- public:
- CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
- virtual ~CacheBlkPrintWrapper() {}
- void print(std::ostream &o, int verbosity = 0,
- const std::string &prefix = "") const;
-};
+ private:
+ /**
+ * Copy of the block's address, used to regenerate tempBlock's address.
+ */
+ Addr _addr;
-/**
- * Wrap a method and present it as a cache block visitor.
- *
- * For example the forEachBlk method in the tag arrays expects a
- * callable object/function as their parameter. This class wraps a
- * method in an object and presents callable object that adheres to
- * the cache block visitor protocol.
- */
-template <typename T, typename BlkType>
-class CacheBlkVisitorWrapper
-{
public:
- typedef bool (T::*visitorPtr)(BlkType &blk);
+ /**
+ * Creates a temporary cache block, with its own storage.
+ * @param size The size (in bytes) of this cache block.
+ */
+ TempCacheBlk(unsigned size) : CacheBlk()
+ {
+ data = new uint8_t[size];
+ }
+ TempCacheBlk(const TempCacheBlk&) = delete;
+ TempCacheBlk& operator=(const TempCacheBlk&) = delete;
+ ~TempCacheBlk() { delete [] data; };
- CacheBlkVisitorWrapper(T &_obj, visitorPtr _visitor)
- : obj(_obj), visitor(_visitor) {}
+ /**
+ * Invalidate the block and clear all state.
+ */
+ void invalidate() override {
+ CacheBlk::invalidate();
- bool operator()(BlkType &blk) {
- return (obj.*visitor)(blk);
+ _addr = MaxAddr;
}
- private:
- T &obj;
- visitorPtr visitor;
-};
-
-/**
- * Cache block visitor that determines if there are dirty blocks in a
- * cache.
- *
- * Use with the forEachBlk method in the tag array to determine if the
- * array contains dirty blocks.
- */
-template <typename BlkType>
-class CacheBlkIsDirtyVisitor
-{
- public:
- CacheBlkIsDirtyVisitor()
- : _isDirty(false) {}
+ void insert(const Addr addr, const bool is_secure,
+ const int src_master_ID=0, const uint32_t task_ID=0) override
+ {
+ // Set block address
+ _addr = addr;
- bool operator()(BlkType &blk) {
- if (blk.isDirty()) {
- _isDirty = true;
- return false;
+ // Set secure state
+ if (is_secure) {
+ status = BlkSecure;
} else {
- return true;
+ status = 0;
}
}
/**
- * Does the array contain a dirty line?
+ * Get block's address.
*
- * \return true if yes, false otherwise.
+ * @return addr Address value.
*/
- bool isDirty() const { return _isDirty; };
+ Addr getAddr() const
+ {
+ return _addr;
+ }
+};
- private:
- bool _isDirty;
+/**
+ * Simple class to provide virtual print() method on cache blocks
+ * without allocating a vtable pointer for every single cache block.
+ * Just wrap the CacheBlk object in an instance of this before passing
+ * to a function that requires a Printable object.
+ */
+class CacheBlkPrintWrapper : public Printable
+{
+ CacheBlk *blk;
+ public:
+ CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
+ virtual ~CacheBlkPrintWrapper() {}
+ void print(std::ostream &o, int verbosity = 0,
+ const std::string &prefix = "") const;
};
-#endif //__CACHE_BLK_HH__
+#endif //__MEM_CACHE_BLK_HH__
projects / gem5.git / blobdiff