/*
+ * Copyright (c) 2012-2014 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Erik Hallnor
+ * Andreas Sandberg
*/
/** @file
#include <list>
#include "base/printable.hh"
-#include "sim/core.hh" // for Tick
-#include "arch/isa_traits.hh" // for Addr
#include "mem/packet.hh"
#include "mem/request.hh"
+#include "sim/core.hh" // for Tick
/**
* Cache block status bit assignments
/** block was referenced */
BlkReferenced = 0x10,
/** block was a hardware prefetch yet unaccessed*/
- BlkHWPrefetched = 0x20
+ BlkHWPrefetched = 0x20,
+ /** block holds data from the secure memory space */
+ BlkSecure = 0x40,
+ /** can the block transition to E? (hasn't been shared with another cache)
+ * used to close a timing gap when handling WriteInvalidate packets */
+ BlkCanGoExclusive = 0x80
};
/**
class CacheBlk
{
public:
+ /** Task Id associated with this block */
+ uint32_t task_id;
+
/** The address space ID of this block. */
int asid;
/** Data block tag value. */
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
- /** Which curTick will this block be accessable */
+ /** Which curTick() will this block be accessable */
Tick whenReady;
/**
*/
int set;
+ /** whether this block has been touched */
+ bool isTouched;
+
/** Number of references to this block since it was brought in. */
int refCount;
+ /** holds the source requestor ID for this block. */
+ int srcMasterId;
+
+ Tick tickInserted;
+
protected:
/**
* Represents that the indicated thread context has a "lock" on
*/
class Lock {
public:
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ int contextId; // locking context
+ Addr lowAddr; // low address of lock range
+ Addr highAddr; // high address of lock range
// check for matching execution context
bool matchesContext(Request *req)
{
- return (cpuNum == req->getCpuNum() &&
- threadNum == req->getThreadNum());
+ Addr req_low = req->getPaddr();
+ Addr req_high = req_low + req->getSize() -1;
+ return (contextId == req->contextId()) &&
+ (req_low >= lowAddr) && (req_high <= highAddr);
+ }
+
+ bool overlapping(Request *req)
+ {
+ Addr req_low = req->getPaddr();
+ Addr req_high = req_low + req->getSize() - 1;
+
+ return (req_low <= highAddr) && (req_high >= lowAddr);
}
Lock(Request *req)
- : cpuNum(req->getCpuNum()), threadNum(req->getThreadNum())
+ : contextId(req->contextId()),
+ lowAddr(req->getPaddr()),
+ highAddr(lowAddr + req->getSize() - 1)
{
}
};
public:
CacheBlk()
- : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
- set(-1), refCount(0)
+ : task_id(ContextSwitchTaskId::Unknown),
+ asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
+ set(-1), isTouched(false), refCount(0),
+ srcMasterId(Request::invldMasterId),
+ tickInserted(0)
{}
/**
whenReady = rhs.whenReady;
set = rhs.set;
refCount = rhs.refCount;
+ task_id = rhs.task_id;
return *this;
}
*/
bool isWritable() const
{
- const int needed_bits = BlkWritable | BlkValid;
+ const State needed_bits = BlkWritable | BlkValid;
return (status & needed_bits) == needed_bits;
}
*/
bool isReadable() const
{
- const int needed_bits = BlkReadable | BlkValid;
+ const State needed_bits = BlkReadable | BlkValid;
return (status & needed_bits) == needed_bits;
}
return (status & BlkValid) != 0;
}
+ /**
+ * Invalidate the block and clear all state.
+ */
+ void invalidate()
+ {
+ status = 0;
+ isTouched = false;
+ clearLoadLocks();
+ }
+
/**
* Check to see if a block has been written.
* @return True if the block is dirty.
* be touched.
* @return True if the block was a hardware prefetch, unaccesed.
*/
- bool isPrefetch() const
+ bool wasPrefetched() const
{
return (status & BlkHWPrefetched) != 0;
}
+ /**
+ * Check if this block holds data from the secure memory space.
+ * @return True if the block holds data from the secure memory space.
+ */
+ bool isSecure() const
+ {
+ return (status & BlkSecure) != 0;
+ }
+
/**
* Track the fact that a local locked was issued to the block. If
* multiple LLs get issued from the same context we could have
*/
void trackLoadLocked(PacketPtr pkt)
{
- assert(pkt->isLocked());
+ assert(pkt->isLLSC());
lockList.push_front(Lock(pkt->req));
}
* Clear the list of valid load locks. Should be called whenever
* block is written to or invalidated.
*/
- void clearLoadLocks() { lockList.clear(); }
+ void clearLoadLocks(Request *req = NULL)
+ {
+ if (!req) {
+ // No request, invaldate all locks to this line
+ lockList.clear();
+ } else {
+ // Only invalidate locks that overlap with this request
+ std::list<Lock>::iterator lock_itr = lockList.begin();
+ while (lock_itr != lockList.end()) {
+ if (lock_itr->overlapping(req)) {
+ lock_itr = lockList.erase(lock_itr);
+ } else {
+ ++lock_itr;
+ }
+ }
+ }
+ }
+
+ /**
+ * Pretty-print a tag, and interpret state bits to readable form
+ * including mapping to a MOESI stat.
+ *
+ * @return string with basic state information
+ */
+ std::string print() const
+ {
+ /**
+ * state M O E S I
+ * writable 1 0 1 0 0
+ * dirty 1 1 0 0 0
+ * valid 1 1 1 1 0
+ *
+ * state writable dirty valid
+ * M 1 1 1
+ * O 0 1 1
+ * E 1 0 1
+ * S 0 0 1
+ * I 0 0 0
+ **/
+ unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
+ char s = '?';
+ switch (state) {
+ case 0b111: s = 'M'; break;
+ case 0b011: s = 'O'; break;
+ case 0b101: s = 'E'; break;
+ case 0b001: s = 'S'; break;
+ case 0b000: s = 'I'; break;
+ default: s = 'T'; break; // @TODO add other types
+ }
+ return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
+ "dirty: %d tag: %x", status, s, isValid(),
+ isWritable(), isReadable(), isDirty(), tag);
+ }
/**
* Handle interaction of load-locked operations and stores.
bool checkWrite(PacketPtr pkt)
{
Request *req = pkt->req;
- if (pkt->isLocked()) {
+ if (pkt->isLLSC()) {
// it's a store conditional... have to check for matching
// load locked.
bool success = false;
}
req->setExtraData(success ? 1 : 0);
- clearLoadLocks();
+ clearLoadLocks(req);
return success;
} else {
// for *all* stores (conditional or otherwise) we have to
// clear the list of load-locks as they're all invalid now.
- clearLoadLocks();
+ clearLoadLocks(req);
return true;
}
}
const std::string &prefix = "") const;
};
+/**
+ * Wrap a method and present it as a cache block visitor.
+ *
+ * For example the forEachBlk method in the tag arrays expects a
+ * callable object/function as their parameter. This class wraps a
+ * method in an object and presents callable object that adheres to
+ * the cache block visitor protocol.
+ */
+template <typename T, typename BlkType>
+class CacheBlkVisitorWrapper
+{
+ public:
+ typedef bool (T::*visitorPtr)(BlkType &blk);
+
+ CacheBlkVisitorWrapper(T &_obj, visitorPtr _visitor)
+ : obj(_obj), visitor(_visitor) {}
+
+ bool operator()(BlkType &blk) {
+ return (obj.*visitor)(blk);
+ }
+
+ private:
+ T &obj;
+ visitorPtr visitor;
+};
+
+/**
+ * Cache block visitor that determines if there are dirty blocks in a
+ * cache.
+ *
+ * Use with the forEachBlk method in the tag array to determine if the
+ * array contains dirty blocks.
+ */
+template <typename BlkType>
+class CacheBlkIsDirtyVisitor
+{
+ public:
+ CacheBlkIsDirtyVisitor()
+ : _isDirty(false) {}
+ bool operator()(BlkType &blk) {
+ if (blk.isDirty()) {
+ _isDirty = true;
+ return false;
+ } else {
+ return true;
+ }
+ }
+
+ /**
+ * Does the array contain a dirty line?
+ *
+ * \return true if yes, false otherwise.
+ */
+ bool isDirty() const { return _isDirty; };
+
+ private:
+ bool _isDirty;
+};
#endif //__CACHE_BLK_HH__
projects / gem5.git / blobdiff