mem: write streaming support via WriteInvalidate promotion

[gem5.git] / src / mem / cache / cache.cc

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 96f9a2e11151d311741e8639e3a467d6033a784a..a5fa0e60d20cd49d050dd45a16f2b20069b84862 100644 (file)
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -36,54 +36,16 @@
  * Cache template instantiations.
  */
 
-#include "mem/config/cache.hh"
-
-#if defined(USE_CACHE_LRU)
-#include "mem/cache/tags/lru.hh"
-#endif
-
-#if defined(USE_CACHE_FALRU)
 #include "mem/cache/tags/fa_lru.hh"
-#endif
-
-#if defined(USE_CACHE_IIC)
-#include "mem/cache/tags/iic.hh"
-#endif
-
-#if defined(USE_CACHE_SPLIT)
-#include "mem/cache/tags/split.hh"
-#endif
-
-#if defined(USE_CACHE_SPLIT_LIFO)
-#include "mem/cache/tags/split_lifo.hh"
-#endif
-
-#include "mem/cache/coherence/simple_coherence.hh"
-
+#include "mem/cache/tags/lru.hh"
+#include "mem/cache/tags/random_repl.hh"
 #include "mem/cache/cache_impl.hh"
 
 // Template Instantiations
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
-
-#if defined(USE_CACHE_FALRU)
-template class Cache<FALRU, SimpleCoherence>;
-#endif
-
-#if defined(USE_CACHE_IIC)
-template class Cache<IIC, SimpleCoherence>;
-#endif
-
-#if defined(USE_CACHE_LRU)
-template class Cache<LRU, SimpleCoherence>;
-#endif
-
-#if defined(USE_CACHE_SPLIT)
-template class Cache<Split, SimpleCoherence>;
-#endif
-
-#if defined(USE_CACHE_SPLIT_LIFO)
-template class Cache<SplitLIFO, SimpleCoherence>;
-#endif
+template class Cache<FALRU>;
+template class Cache<LRU>;
+template class Cache<RandomRepl>;
 
 #endif //DOXYGEN_SHOULD_SKIP_THIS