* Authors: Erik Hallnor
* Dave Greene
* Steve Reinhardt
+ * Ron Dreslinski
*/
/**
#ifndef __CACHE_HH__
#define __CACHE_HH__
+#include "base/compression/base.hh"
#include "base/misc.hh" // fatal, panic, and warn
#include "cpu/smt.hh" // SMT_MAX_THREADS
#include "mem/cache/base_cache.hh"
-#include "mem/cache/prefetch/prefetcher.hh"
+#include "mem/cache/cache_blk.hh"
+#include "mem/cache/miss/mshr.hh"
-//Forward decleration
-class MSHR;
+#include "sim/eventq.hh"
+//Forward decleration
+class BasePrefetcher;
/**
* A template-policy based cache. The behavior of the cache can be altered by
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering, class Coherence>
+template <class TagStore, class Coherence>
class Cache : public BaseCache
{
public:
/** Define the type of cache block to use. */
typedef typename TagStore::BlkType BlkType;
+ /** A typedef for a list of BlkType pointers. */
+ typedef typename TagStore::BlkList BlkList;
bool prefetchAccess;
+
protected:
+ class CpuSidePort : public CachePort
+ {
+ public:
+ CpuSidePort(const std::string &_name,
+ Cache<TagStore,Coherence> *_cache);
+
+ // BaseCache::CachePort just has a BaseCache *; this function
+ // lets us get back the type info we lost when we stored the
+ // cache pointer there.
+ Cache<TagStore,Coherence> *myCache() {
+ return static_cast<Cache<TagStore,Coherence> *>(cache);
+ }
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
+ virtual bool recvTiming(PacketPtr pkt);
+
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ virtual void recvFunctional(PacketPtr pkt);
+ };
+
+ class MemSidePort : public CachePort
+ {
+ public:
+ MemSidePort(const std::string &_name,
+ Cache<TagStore,Coherence> *_cache);
+
+ // BaseCache::CachePort just has a BaseCache *; this function
+ // lets us get back the type info we lost when we stored the
+ // cache pointer there.
+ Cache<TagStore,Coherence> *myCache() {
+ return static_cast<Cache<TagStore,Coherence> *>(cache);
+ }
+
+ void sendPacket();
+
+ void processSendEvent();
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
+ virtual bool recvTiming(PacketPtr pkt);
+
+ virtual void recvRetry();
+
+ virtual Tick recvAtomic(PacketPtr pkt);
+
+ virtual void recvFunctional(PacketPtr pkt);
+
+ typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
+ SendEvent;
+ };
+
/** Tag and data Storage */
TagStore *tags;
- /** Miss and Writeback handler */
- Buffering *missQueue;
+
/** Coherence protocol. */
Coherence *coherence;
/** Prefetcher */
- Prefetcher<TagStore, Buffering> *prefetcher;
-
- /** Do fast copies in this cache. */
- bool doCopy;
-
- /** Block on a delayed copy. */
- bool blockOnCopy;
+ BasePrefetcher *prefetcher;
/**
* The clock ratio of the outgoing bus.
*/
int hitLatency;
- /**
- * A permanent mem req to always be used to cause invalidations.
- * Used to append to target list, to cause an invalidation.
- */
- Packet * invalidatePkt;
- Request *invalidateReq;
+ /**
+ * Can this cache should allocate a block on a line-sized write miss.
+ */
+ const bool doFastWrites;
+
+ const bool prefetchMiss;
/**
- * Temporarily move a block into a MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
+ * Handle a replacement for the given request.
+ * @param blk A pointer to the block, usually NULL
+ * @param pkt The memory request to satisfy.
+ * @param new_state The new state of the block.
+ * @param writebacks A list to store any generated writebacks.
*/
- void pseudoFill(Addr addr);
+ BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
+ CacheBlk::State new_state, PacketList &writebacks);
/**
- * Temporarily move a block into an existing MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
+ * Does all the processing necessary to perform the provided request.
+ * @param pkt The memory request to perform.
+ * @param lat The latency of the access.
+ * @param writebacks List for any writebacks that need to be performed.
+ * @param update True if the replacement data should be updated.
+ * @return Pointer to the cache block touched by the request. NULL if it
+ * was a miss.
*/
- void pseudoFill(MSHR *mshr);
+ bool access(PacketPtr pkt, BlkType *&blk, int &lat);
+
+ /**
+ *Handle doing the Compare and Swap function for SPARC.
+ */
+ void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+
+ /**
+ * Populates a cache block and handles all outstanding requests for the
+ * satisfied fill request. This version takes two memory requests. One
+ * contains the fill data, the other is an optional target to satisfy.
+ * Used for Cache::probe.
+ * @param pkt The memory request with the fill data.
+ * @param blk The cache block if it already exists.
+ * @param writebacks List for any writebacks that need to be performed.
+ * @return Pointer to the new cache block.
+ */
+ BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ PacketList &writebacks);
+
+ bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
+ bool satisfyTarget(MSHR::Target *target, BlkType *blk);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+
+ void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data);
+
+ /**
+ * Sets the blk to the new state.
+ * @param blk The cache block being snooped.
+ * @param new_state The new coherence state for the block.
+ */
+ void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing);
+
+ /**
+ * Create a writeback request for the given block.
+ * @param blk The block to writeback.
+ * @return The writeback request for the block.
+ */
+ PacketPtr writebackBlk(BlkType *blk);
public:
{
public:
TagStore *tags;
- Buffering *missQueue;
Coherence *coherence;
- bool doCopy;
- bool blockOnCopy;
BaseCache::Params baseParams;
- Prefetcher<TagStore, Buffering> *prefetcher;
+ BasePrefetcher*prefetcher;
bool prefetchAccess;
- int hitLatency;
-
- Params(TagStore *_tags, Buffering *mq, Coherence *coh,
- bool do_copy, BaseCache::Params params,
- Prefetcher<TagStore, Buffering> *_prefetcher,
- bool prefetch_access, int hit_latency)
- : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
- blockOnCopy(false), baseParams(params),
+ const bool doFastWrites;
+ const bool prefetchMiss;
+
+ Params(TagStore *_tags, Coherence *coh,
+ BaseCache::Params params,
+ BasePrefetcher *_prefetcher,
+ bool prefetch_access, int hit_latency,
+ bool do_fast_writes,
+ bool prefetch_miss)
+ : tags(_tags), coherence(coh),
+ baseParams(params),
prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- hitLatency(hit_latency)
+ doFastWrites(do_fast_writes),
+ prefetchMiss(prefetch_miss)
{
}
};
/** Instantiates a basic cache object. */
Cache(const std::string &_name, Params ¶ms);
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
- bool isCpuSide);
-
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
-
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
-
- virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual void deletePortRefs(Port *p);
void regStats();
* @param pkt The request to perform.
* @return The result of the access.
*/
- bool access(Packet * &pkt);
+ bool timingAccess(PacketPtr pkt);
/**
- * Selects a request to send on the bus.
- * @return The memory request to service.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- virtual Packet * getPacket();
+ Tick atomicAccess(PacketPtr pkt);
/**
- * Was the request was sent successfully?
- * @param pkt The request.
- * @param success True if the request was sent successfully.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
+ void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The request being responded to.
*/
- void handleResponse(Packet * &pkt);
+ void handleResponse(PacketPtr pkt);
/**
- * Start handling a copy transaction.
- * @param pkt The copy request to perform.
+ * Snoops bus transactions to maintain coherence.
+ * @param pkt The current bus transaction.
*/
- void startCopy(Packet * &pkt);
+ void snoopTiming(PacketPtr pkt);
/**
- * Handle a delayed copy transaction.
- * @param pkt The delayed copy request to continue.
- * @param addr The address being responded to.
- * @param blk The block of the current response.
- * @param mshr The mshr being handled.
+ * Snoop for the provided request in the cache and return the estimated
+ * time of completion.
+ * @param pkt The memory request to snoop
+ * @return The estimated completion time.
*/
- void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
+ Tick snoopAtomic(PacketPtr pkt);
/**
- * Selects a coherence message to forward to lower levels of the hierarchy.
- * @return The coherence message to forward.
+ * Squash all requests associated with specified thread.
+ * intended for use by I-cache.
+ * @param threadNum The thread to squash.
*/
- virtual Packet * getCoherencePacket();
+ void squash(int threadNum);
/**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
+ * Allocate a new MSHR or write buffer to handle a miss.
+ * @param pkt The access that missed.
+ * @param time The time to continue processing the miss.
+ * @param isFill Whether to fetch & allocate a block
+ * or just forward the request.
*/
- void snoop(Packet * &pkt);
+ MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus);
- void snoopResponse(Packet * &pkt);
+ /**
+ * Selects a outstanding request to service.
+ * @return The request to service, NULL if none found.
+ */
+ PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
+ bool needsExclusive);
+ MSHR *getNextMSHR();
+ PacketPtr getTimingPacket();
/**
- * Invalidates the block containing address if found.
- * @param addr The address to look for.
- * @param asid The address space ID of the address.
- * @todo Is this function necessary?
+ * Marks a request as in service (sent on the bus). This can have side
+ * effect since storage for no response commands is deallocated once they
+ * are successfully sent.
+ * @param pkt The request that was sent on the bus.
*/
- void invalidateBlk(Addr addr);
+ void markInService(MSHR *mshr);
/**
- * Squash all requests associated with specified thread.
- * intended for use by I-cache.
- * @param threadNum The thread to squash.
+ * Perform the given writeback request.
+ * @param pkt The writeback request.
*/
- void squash(int threadNum)
- {
- missQueue->squash(threadNum);
- }
+ void doWriteback(PacketPtr pkt);
/**
- * Return the number of outstanding misses in a Cache.
- * Default returns 0.
- *
- * @retval unsigned The number of missing still outstanding.
+ * Return whether there are any outstanding misses.
*/
- unsigned outstandingMisses() const
+ bool outstandingMisses() const
{
- return missQueue->getMisses();
+ return mshrQueue.allocated != 0;
}
- /**
- * Perform the access specified in the request and return the estimated
- * time of completion. This function can either update the hierarchy state
- * or just perform the access wherever the data is found depending on the
- * state of the update flag.
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
- */
- Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
+ CacheBlk *findBlock(Addr addr) {
+ return tags->findBlock(addr);
+ }
- /**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @todo Can a snoop probe not change state?
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
- */
- Tick snoopProbe(Packet * &pkt);
+ bool inCache(Addr addr) {
+ return (tags->findBlock(addr) != 0);
+ }
+
+ bool inMissQueue(Addr addr) {
+ return (mshrQueue.findMatch(addr) != 0);
+ }
};
#endif // __CACHE_HH__
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