/** Prefetcher */
Prefetcher<TagStore, Buffering> *prefetcher;
- /** Do fast copies in this cache. */
- bool doCopy;
-
- /** Block on a delayed copy. */
- bool blockOnCopy;
-
/**
* The clock ratio of the outgoing bus.
* Used for calculating critical word first.
* Used to append to target list, to cause an invalidation.
*/
Packet * invalidatePkt;
-
- /**
- * Temporarily move a block into a MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(Addr addr, int asid);
-
- /**
- * Temporarily move a block into an existing MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(MSHR *mshr);
+ Request *invalidateReq;
public:
TagStore *tags;
Buffering *missQueue;
Coherence *coherence;
- bool doCopy;
- bool blockOnCopy;
BaseCache::Params baseParams;
Prefetcher<TagStore, Buffering> *prefetcher;
bool prefetchAccess;
int hitLatency;
Params(TagStore *_tags, Buffering *mq, Coherence *coh,
- bool do_copy, BaseCache::Params params,
+ BaseCache::Params params,
Prefetcher<TagStore, Buffering> *_prefetcher,
bool prefetch_access, int hit_latency)
- : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
- blockOnCopy(false), baseParams(params),
+ : tags(_tags), missQueue(mq), coherence(coh),
+ baseParams(params),
prefetcher(_prefetcher), prefetchAccess(prefetch_access),
hitLatency(hit_latency)
{
* @param pkt The request.
* @param success True if the request was sent successfully.
*/
- virtual void sendResult(Packet * &pkt, bool success);
+ virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
/**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The request being responded to.
- */
- void handleResponse(Packet * &pkt);
-
- /**
- * Start handling a copy transaction.
- * @param pkt The copy request to perform.
+ * Was the CSHR request was sent successfully?
+ * @param pkt The request.
+ * @param success True if the request was sent successfully.
*/
- void startCopy(Packet * &pkt);
+ virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
/**
- * Handle a delayed copy transaction.
- * @param pkt The delayed copy request to continue.
- * @param addr The address being responded to.
- * @param blk The block of the current response.
- * @param mshr The mshr being handled.
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The request being responded to.
*/
- void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
+ void handleResponse(Packet * &pkt);
/**
* Selects a coherence message to forward to lower levels of the hierarchy.
* @param asid The address space ID of the address.
* @todo Is this function necessary?
*/
- void invalidateBlk(Addr addr, int asid);
+ void invalidateBlk(Addr addr);
/**
* Squash all requests associated with specified thread.
* request.
* @return The estimated completion time.
*/
- Tick probe(Packet * &pkt, bool update);
+ Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
* request.
* @return The estimated completion time.
*/
- Tick snoopProbe(Packet * &pkt, bool update);
+ Tick snoopProbe(Packet * &pkt);
};
#endif // __CACHE_HH__