mem: write streaming support via WriteInvalidate promotion

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 60f3650e7222260720fe01e747e932413aaf91ca..12fb3b0f0ce4bee46eb759833018e95fed585a78 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2014 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -180,6 +180,11 @@ class Cache : public BaseCache
      */
     const bool doFastWrites;
 
+    /**
+     * Turn line-sized writes into WriteInvalidate transactions.
+     */
+    void promoteWholeLineWrites(PacketPtr pkt);
+
     /**
      * Notify the prefetcher on every access, not just misses.
      */
@@ -195,9 +200,9 @@ class Cache : public BaseCache
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.
+     * @param blk The cache block to be updated.
      * @param lat The latency of the access.
      * @param writebacks List for any writebacks that need to be performed.
-     * @param update True if the replacement data should be updated.
      * @return Boolean indicating whether the request was satisfied.
      */
     bool access(PacketPtr pkt, BlkType *&blk,