/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2014 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
virtual void recvFunctional(PacketPtr pkt);
- virtual unsigned deviceBlockSize() const
- { return cache->getBlockSize(); }
-
virtual AddrRangeList getAddrRanges() const;
public:
virtual void recvFunctionalSnoop(PacketPtr pkt);
- virtual unsigned deviceBlockSize() const
- { return cache->getBlockSize(); }
-
public:
MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
*/
const bool doFastWrites;
+ /**
+ * Turn line-sized writes into WriteInvalidate transactions.
+ */
+ void promoteWholeLineWrites(PacketPtr pkt);
+
/**
* Notify the prefetcher on every access, not just misses.
*/
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
+ * @param blk The cache block to be updated.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
- * @param update True if the replacement data should be updated.
* @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
void cmpAndSwap(BlkType *blk, PacketPtr pkt);
/**
- * Find a block frame for new block at address addr, assuming that
- * the block is not currently in the cache. Append writebacks if
- * any to provided packet list. Return free block frame. May
- * return NULL if there are no replaceable blocks at the moment.
+ * Find a block frame for new block at address addr targeting the
+ * given security space, assuming that the block is not currently
+ * in the cache. Append writebacks if any to provided packet
+ * list. Return free block frame. May return NULL if there are
+ * no replaceable blocks at the moment.
*/
- BlkType *allocateBlock(Addr addr, PacketList &writebacks);
+ BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
BlkType *handleFill(PacketPtr pkt, BlkType *blk,
PacketList &writebacks);
+
+ /**
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
+ */
+ bool recvTimingReq(PacketPtr pkt);
+
+ /**
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The response packet
+ */
+ void recvTimingResp(PacketPtr pkt);
+
+ /**
+ * Snoops bus transactions to maintain coherence.
+ * @param pkt The current bus transaction.
+ */
+ void recvTimingSnoopReq(PacketPtr pkt);
+
+ /**
+ * Handle a snoop response.
+ * @param pkt Snoop response packet
+ */
+ void recvTimingSnoopResp(PacketPtr pkt);
+
+ /**
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The number of ticks required for the access.
+ */
+ Tick recvAtomic(PacketPtr pkt);
+
+ /**
+ * Snoop for the provided request in the cache and return the estimated
+ * time taken.
+ * @param pkt The memory request to snoop
+ * @return The number of ticks required for the snoop.
+ */
+ Tick recvAtomicSnoop(PacketPtr pkt);
+
+ /**
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @param fromCpuSide from the CPU side port or the memory side port
+ */
+ void functionalAccess(PacketPtr pkt, bool fromCpuSide);
+
void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
bool deferred_response = false,
bool pending_downgrade = false);
*/
void uncacheableFlush(PacketPtr pkt);
- public:
- /** Instantiates a basic cache object. */
- Cache(const Params *p, TagStore *tags);
-
- void regStats();
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
- */
- bool timingAccess(PacketPtr pkt);
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The number of ticks required for the access.
- */
- Tick atomicAccess(PacketPtr pkt);
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @param fromCpuSide from the CPU side port or the memory side port
- */
- void functionalAccess(PacketPtr pkt, bool fromCpuSide);
-
- /**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The request being responded to.
- */
- void handleResponse(PacketPtr pkt);
-
- /**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
- */
- void snoopTiming(PacketPtr pkt);
-
- /**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @param pkt The memory request to snoop
- * @return The number of cycles required for the snoop.
- */
- Cycles snoopAtomic(PacketPtr pkt);
-
/**
* Squash all requests associated with specified thread.
* intended for use by I-cache.
* current request in cpu_pkt should just be forwarded on.
*/
PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive);
+ bool needsExclusive) const;
/**
* Return the next MSHR to service, either a pending miss from the
return mshrQueue.allocated != 0;
}
- CacheBlk *findBlock(Addr addr) {
- return tags->findBlock(addr);
+ CacheBlk *findBlock(Addr addr, bool is_secure) const {
+ return tags->findBlock(addr, is_secure);
}
- bool inCache(Addr addr) {
- return (tags->findBlock(addr) != 0);
+ bool inCache(Addr addr, bool is_secure) const {
+ return (tags->findBlock(addr, is_secure) != 0);
}
- bool inMissQueue(Addr addr) {
- return (mshrQueue.findMatch(addr) != 0);
+ bool inMissQueue(Addr addr, bool is_secure) const {
+ return (mshrQueue.findMatch(addr, is_secure) != 0);
}
/**
* Find next request ready time from among possible sources.
*/
- Tick nextMSHRReadyTime();
+ Tick nextMSHRReadyTime() const;
+
+ public:
+ /** Instantiates a basic cache object. */
+ Cache(const Params *p);
+
+ /** Non-default destructor is needed to deallocate memory. */
+ virtual ~Cache();
+
+ void regStats();
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.