/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2014 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* Dave Greene
* Steve Reinhardt
* Ron Dreslinski
+ * Andreas Hansson
*/
/**
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore.
+ * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
*/
template <class TagStore>
class Cache : public BaseCache
typedef typename TagStore::BlkList BlkList;
protected:
+ typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
- class CpuSidePort : public CachePort
+ /**
+ * The CPU-side port extends the base cache slave port with access
+ * functions for functional, atomic and timing requests.
+ */
+ class CpuSidePort : public CacheSlavePort
{
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- const std::string &_label);
+ private:
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual AddrRangeList getAddrRanges();
+ protected:
- virtual bool recvTiming(PacketPtr pkt);
+ virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+ virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ virtual AddrRangeList getAddrRanges() const;
+
+ public:
+
+ CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
+
};
- class MemSidePort : public CachePort
+ /**
+ * Override the default behaviour of sendDeferredPacket to enable
+ * the memory-side cache port to also send requests based on the
+ * current MSHR status. This queue has a pointer to our specific
+ * cache implementation and is used by the MemSidePort.
+ */
+ class MemSidePacketQueue : public MasterPacketQueue
{
+
+ protected:
+
+ Cache<TagStore> &cache;
+
public:
- MemSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- const std::string &_label);
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
+ MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
+ const std::string &label) :
+ MasterPacketQueue(cache, port, label), cache(cache) { }
+
+ /**
+ * Override the normal sendDeferredPacket and do not only
+ * consider the transmit list (used for responses), but also
+ * requests.
+ */
+ virtual void sendDeferredPacket();
+
+ };
+
+ /**
+ * The memory-side port extends the base cache master port with
+ * access functions for functional, atomic and timing snoops.
+ */
+ class MemSidePort : public CacheMasterPort
+ {
+ private:
- void sendPacket();
+ /** The cache-specific queue. */
+ MemSidePacketQueue _queue;
- void processSendEvent();
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual bool isSnooping();
+ protected:
- virtual bool recvTiming(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
- virtual void recvRetry();
+ virtual bool recvTimingResp(PacketPtr pkt);
- virtual Tick recvAtomic(PacketPtr pkt);
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
- virtual void recvFunctional(PacketPtr pkt);
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+
+ public:
- typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
- SendEvent;
+ MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
};
/** Tag and data Storage */
*/
const bool doFastWrites;
+ /**
+ * Turn line-sized writes into WriteInvalidate transactions.
+ */
+ void promoteWholeLineWrites(PacketPtr pkt);
+
/**
* Notify the prefetcher on every access, not just misses.
*/
const bool prefetchOnAccess;
+ /**
+ * @todo this is a temporary workaround until the 4-phase code is committed.
+ * upstream caches need this packet until true is returned, so hold it for
+ * deletion until a subsequent call
+ */
+ std::vector<PacketPtr> pendingDelete;
+
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
+ * @param blk The cache block to be updated.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
- * @param update True if the replacement data should be updated.
* @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
- int &lat, PacketList &writebacks);
+ Cycles &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
void cmpAndSwap(BlkType *blk, PacketPtr pkt);
/**
- * Find a block frame for new block at address addr, assuming that
- * the block is not currently in the cache. Append writebacks if
- * any to provided packet list. Return free block frame. May
- * return NULL if there are no replaceable blocks at the moment.
+ * Find a block frame for new block at address addr targeting the
+ * given security space, assuming that the block is not currently
+ * in the cache. Append writebacks if any to provided packet
+ * list. Return free block frame. May return NULL if there are
+ * no replaceable blocks at the moment.
*/
- BlkType *allocateBlock(Addr addr, PacketList &writebacks);
+ BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
BlkType *handleFill(PacketPtr pkt, BlkType *blk,
PacketList &writebacks);
- void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
- bool deferred_response = false,
- bool pending_downgrade = false);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
-
- void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
- bool already_copied, bool pending_inval);
/**
- * Sets the blk to the new state.
- * @param blk The cache block being snooped.
- * @param new_state The new coherence state for the block.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- void handleSnoop(PacketPtr ptk, BlkType *blk,
- bool is_timing, bool is_deferred, bool pending_inval);
+ bool recvTimingReq(PacketPtr pkt);
/**
- * Create a writeback request for the given block.
- * @param blk The block to writeback.
- * @return The writeback request for the block.
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The response packet
*/
- PacketPtr writebackBlk(BlkType *blk);
+ void recvTimingResp(PacketPtr pkt);
- public:
- /** Instantiates a basic cache object. */
- Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
-
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ /**
+ * Snoops bus transactions to maintain coherence.
+ * @param pkt The current bus transaction.
+ */
+ void recvTimingSnoopReq(PacketPtr pkt);
- void regStats();
+ /**
+ * Handle a snoop response.
+ * @param pkt Snoop response packet
+ */
+ void recvTimingSnoopResp(PacketPtr pkt);
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @return The number of ticks required for the access.
*/
- bool timingAccess(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt);
/**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
+ * Snoop for the provided request in the cache and return the estimated
+ * time taken.
+ * @param pkt The memory request to snoop
+ * @return The number of ticks required for the snoop.
*/
- Tick atomicAccess(PacketPtr pkt);
+ Tick recvAtomicSnoop(PacketPtr pkt);
/**
* Performs the access specified by the request.
*/
void functionalAccess(PacketPtr pkt, bool fromCpuSide);
+ void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+
+ void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
+ bool already_copied, bool pending_inval);
+
/**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The request being responded to.
+ * Sets the blk to the new state.
+ * @param blk The cache block being snooped.
+ * @param new_state The new coherence state for the block.
*/
- void handleResponse(PacketPtr pkt);
+ void handleSnoop(PacketPtr ptk, BlkType *blk,
+ bool is_timing, bool is_deferred, bool pending_inval);
/**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
+ * Create a writeback request for the given block.
+ * @param blk The block to writeback.
+ * @return The writeback request for the block.
*/
- void snoopTiming(PacketPtr pkt);
+ PacketPtr writebackBlk(BlkType *blk);
+
+
+ void memWriteback();
+ void memInvalidate();
+ bool isDirty() const;
/**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @param pkt The memory request to snoop
- * @return The estimated completion time.
+ * Cache block visitor that writes back dirty cache blocks using
+ * functional writes.
+ *
+ * \return Always returns true.
*/
- Tick snoopAtomic(PacketPtr pkt);
+ bool writebackVisitor(BlkType &blk);
+ /**
+ * Cache block visitor that invalidates all blocks in the cache.
+ *
+ * @warn Dirty cache lines will not be written back to memory.
+ *
+ * \return Always returns true.
+ */
+ bool invalidateVisitor(BlkType &blk);
+
+ /**
+ * Flush a cache line due to an uncacheable memory access to the
+ * line.
+ *
+ * @note This shouldn't normally happen, but we need to handle it
+ * since some architecture models don't implement cache
+ * maintenance operations. We won't even try to get a decent
+ * timing here since the line should have been flushed earlier by
+ * a cache maintenance operation.
+ */
+ void uncacheableFlush(PacketPtr pkt);
/**
* Squash all requests associated with specified thread.
* current request in cpu_pkt should just be forwarded on.
*/
PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive);
+ bool needsExclusive) const;
/**
* Return the next MSHR to service, either a pending miss from the
*/
void markInService(MSHR *mshr, PacketPtr pkt = 0);
- /**
- * Perform the given writeback request.
- * @param pkt The writeback request.
- */
- void doWriteback(PacketPtr pkt);
-
/**
* Return whether there are any outstanding misses.
*/
return mshrQueue.allocated != 0;
}
- CacheBlk *findBlock(Addr addr) {
- return tags->findBlock(addr);
+ CacheBlk *findBlock(Addr addr, bool is_secure) const {
+ return tags->findBlock(addr, is_secure);
}
- bool inCache(Addr addr) {
- return (tags->findBlock(addr) != 0);
+ bool inCache(Addr addr, bool is_secure) const {
+ return (tags->findBlock(addr, is_secure) != 0);
}
- bool inMissQueue(Addr addr) {
- return (mshrQueue.findMatch(addr) != 0);
+ bool inMissQueue(Addr addr, bool is_secure) const {
+ return (mshrQueue.findMatch(addr, is_secure) != 0);
}
/**
* Find next request ready time from among possible sources.
*/
- Tick nextMSHRReadyTime();
+ Tick nextMSHRReadyTime() const;
+
+ public:
+ /** Instantiates a basic cache object. */
+ Cache(const Params *p);
+
+ /** Non-default destructor is needed to deallocate memory. */
+ virtual ~Cache();
+
+ void regStats();
+
+ /** serialize the state of the caches
+ * We currently don't support checkpointing cache state, so this panics.
+ */
+ virtual void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
#endif // __CACHE_HH__
projects / gem5.git / blobdiff