mem: write streaming support via WriteInvalidate promotion

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index d27dfc5e260a492768daa269aed466e826599b10..12fb3b0f0ce4bee46eb759833018e95fed585a78 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2014 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -99,9 +99,6 @@ class Cache : public BaseCache
 
         virtual void recvFunctional(PacketPtr pkt);
 
-        virtual unsigned deviceBlockSize() const
-        { return cache->getBlockSize(); }
-
         virtual AddrRangeList getAddrRanges() const;
 
       public:
@@ -163,9 +160,6 @@ class Cache : public BaseCache
 
         virtual void recvFunctionalSnoop(PacketPtr pkt);
 
-        virtual unsigned deviceBlockSize() const
-        { return cache->getBlockSize(); }
-
       public:
 
         MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
@@ -186,6 +180,11 @@ class Cache : public BaseCache
      */
     const bool doFastWrites;
 
+    /**
+     * Turn line-sized writes into WriteInvalidate transactions.
+     */
+    void promoteWholeLineWrites(PacketPtr pkt);
+
     /**
      * Notify the prefetcher on every access, not just misses.
      */
@@ -201,9 +200,9 @@ class Cache : public BaseCache
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.
+     * @param blk The cache block to be updated.
      * @param lat The latency of the access.
      * @param writebacks List for any writebacks that need to be performed.
-     * @param update True if the replacement data should be updated.
      * @return Boolean indicating whether the request was satisfied.
      */
     bool access(PacketPtr pkt, BlkType *&blk,
@@ -215,12 +214,13 @@ class Cache : public BaseCache
     void cmpAndSwap(BlkType *blk, PacketPtr pkt);
 
     /**
-     * Find a block frame for new block at address addr, assuming that
-     * the block is not currently in the cache.  Append writebacks if
-     * any to provided packet list.  Return free block frame.  May
-     * return NULL if there are no replaceable blocks at the moment.
+     * Find a block frame for new block at address addr targeting the
+     * given security space, assuming that the block is not currently
+     * in the cache.  Append writebacks if any to provided packet
+     * list.  Return free block frame.  May return NULL if there are
+     * no replaceable blocks at the moment.
      */
-    BlkType *allocateBlock(Addr addr, PacketList &writebacks);
+    BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
 
     /**
      * Populates a cache block and handles all outstanding requests for the
@@ -263,17 +263,17 @@ class Cache : public BaseCache
     /**
      * Performs the access specified by the request.
      * @param pkt The request to perform.
-     * @return The number of cycles required for the access.
+     * @return The number of ticks required for the access.
      */
-    Cycles recvAtomic(PacketPtr pkt);
+    Tick recvAtomic(PacketPtr pkt);
 
     /**
      * Snoop for the provided request in the cache and return the estimated
-     * time of completion.
+     * time taken.
      * @param pkt The memory request to snoop
-     * @return The number of cycles required for the snoop.
+     * @return The number of ticks required for the snoop.
      */
-    Cycles recvAtomicSnoop(PacketPtr pkt);
+    Tick recvAtomicSnoop(PacketPtr pkt);
 
     /**
      * Performs the access specified by the request.
@@ -390,16 +390,16 @@ class Cache : public BaseCache
         return mshrQueue.allocated != 0;
     }
 
-    CacheBlk *findBlock(Addr addr) const {
-        return tags->findBlock(addr);
+    CacheBlk *findBlock(Addr addr, bool is_secure) const {
+        return tags->findBlock(addr, is_secure);
     }
 
-    bool inCache(Addr addr) const {
-        return (tags->findBlock(addr) != 0);
+    bool inCache(Addr addr, bool is_secure) const {
+        return (tags->findBlock(addr, is_secure) != 0);
     }
 
-    bool inMissQueue(Addr addr) const {
-        return (mshrQueue.findMatch(addr) != 0);
+    bool inMissQueue(Addr addr, bool is_secure) const {
+        return (mshrQueue.findMatch(addr, is_secure) != 0);
     }
 
     /**
@@ -409,7 +409,10 @@ class Cache : public BaseCache
 
   public:
     /** Instantiates a basic cache object. */
-    Cache(const Params *p, TagStore *tags);
+    Cache(const Params *p);
+
+    /** Non-default destructor is needed to deallocate memory. */
+    virtual ~Cache();
 
     void regStats();