/** Prefetcher */
Prefetcher<TagStore, Buffering> *prefetcher;
- /** Do fast copies in this cache. */
- bool doCopy;
-
- /** Block on a delayed copy. */
- bool blockOnCopy;
-
/**
* The clock ratio of the outgoing bus.
* Used for calculating critical word first.
* A permanent mem req to always be used to cause invalidations.
* Used to append to target list, to cause an invalidation.
*/
- Packet * invalidatePkt;
-
- /**
- * Temporarily move a block into a MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(Addr addr, int asid);
-
- /**
- * Temporarily move a block into an existing MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(MSHR *mshr);
+ PacketPtr invalidatePkt;
+ Request *invalidateReq;
public:
TagStore *tags;
Buffering *missQueue;
Coherence *coherence;
- bool doCopy;
- bool blockOnCopy;
BaseCache::Params baseParams;
Prefetcher<TagStore, Buffering> *prefetcher;
bool prefetchAccess;
int hitLatency;
Params(TagStore *_tags, Buffering *mq, Coherence *coh,
- bool do_copy, BaseCache::Params params,
+ BaseCache::Params params,
Prefetcher<TagStore, Buffering> *_prefetcher,
bool prefetch_access, int hit_latency)
- : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
- blockOnCopy(false), baseParams(params),
+ : tags(_tags), missQueue(mq), coherence(coh),
+ baseParams(params),
prefetcher(_prefetcher), prefetchAccess(prefetch_access),
hitLatency(hit_latency)
{
/** Instantiates a basic cache object. */
Cache(const std::string &_name, Params ¶ms);
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+ virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
bool isCpuSide);
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
+ virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
+ virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
- bool access(Packet * &pkt);
+ bool access(PacketPtr &pkt);
/**
* Selects a request to send on the bus.
* @return The memory request to service.
*/
- Packet * getPacket();
+ virtual PacketPtr getPacket();
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
- void sendResult(Packet * &pkt, bool success);
+ virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
/**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
- */
- void handleResponse(Packet * &pkt);
-
- /**
- * Start handling a copy transaction.
- * @param req The copy request to perform.
+ * Was the CSHR request was sent successfully?
+ * @param pkt The request.
+ * @param success True if the request was sent successfully.
*/
- void startCopy(Packet * &pkt);
+ virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
/**
- * Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
- * @param addr The address being responded to.
- * @param blk The block of the current response.
- * @param mshr The mshr being handled.
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The request being responded to.
*/
- void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
+ void handleResponse(PacketPtr &pkt);
/**
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
- Packet * getCoherenceReq();
+ virtual PacketPtr getCoherencePacket();
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
- void snoop(Packet * &pkt);
+ void snoop(PacketPtr &pkt);
- void snoopResponse(Packet * &pkt);
+ void snoopResponse(PacketPtr &pkt);
/**
* Invalidates the block containing address if found.
* @param asid The address space ID of the address.
* @todo Is this function necessary?
*/
- void invalidateBlk(Addr addr, int asid);
+ void invalidateBlk(Addr addr);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum)
{
return missQueue->getMisses();
}
- /**
- * Send a response to the slave interface.
- * @param req The request being responded to.
- * @param time The time the response is ready.
- */
- void respond(Packet * &pkt, Tick time)
- {
- //si->respond(pkt,time);
- cpuSidePort->sendAtomic(pkt);
- }
-
/**
* Perform the access specified in the request and return the estimated
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
*/
- Tick probe(Packet * &pkt, bool update);
+ Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
*/
- Tick snoopProbe(Packet * &pkt, bool update);
+ Tick snoopProbe(PacketPtr &pkt);
};
#endif // __CACHE_HH__
projects / gem5.git / blobdiff