Now timing reads work in single level of cache with simple cpu

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1243c9d9ecd151000cfe61fddfa03586e20dafb1..2e77444a08cccd5e654bfc7045e5ed3a34743a14 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -168,7 +168,7 @@ class Cache : public BaseCache
      * Selects a request to send on the bus.
      * @return The memory request to service.
      */
-    Packet * getPacket();
+    virtual Packet * getPacket();
 
     /**
      * Was the request was sent successfully?
@@ -241,17 +241,6 @@ class Cache : public BaseCache
         return missQueue->getMisses();
     }
 
-    /**
-     * Send a response to the slave interface.
-     * @param req The request being responded to.
-     * @param time The time the response is ready.
-     */
-    void respond(Packet * &pkt, Tick time)
-    {
-        //si->respond(pkt,time);
-        cpuSidePort->sendAtomic(pkt);
-    }
-
     /**
      * Perform the access specified in the request and return the estimated
      * time of completion. This function can either update the hierarchy state