Now timing reads work in single level of cache with simple cpu

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 78e87479bb0846437a2fd2b0ea2ac78d2354f977..2e77444a08cccd5e654bfc7045e5ed3a34743a14 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -44,8 +44,9 @@
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/prefetch/prefetcher.hh"
 
-// forward declarations
-class Bus;
+//Forward decleration
+class MSHR;
+
 
 /**
  * A template-policy based cache. The behavior of the cache can be altered by
@@ -92,6 +93,11 @@ class Cache : public BaseCache
       */
     int busWidth;
 
+    /**
+     * The latency of a hit in this device.
+     */
+    int hitLatency;
+
      /**
       * A permanent mem req to always be used to cause invalidations.
       * Used to append to target list, to cause an invalidation.
@@ -121,24 +127,33 @@ class Cache : public BaseCache
         bool doCopy;
         bool blockOnCopy;
         BaseCache::Params baseParams;
-        Bus *in;
-        Bus *out;
         Prefetcher<TagStore, Buffering> *prefetcher;
         bool prefetchAccess;
+        int hitLatency;
 
         Params(TagStore *_tags, Buffering *mq, Coherence *coh,
-               bool do_copy, BaseCache::Params params, Bus * in_bus,
-               Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
-               bool prefetch_access)
+               bool do_copy, BaseCache::Params params,
+               Prefetcher<TagStore, Buffering> *_prefetcher,
+               bool prefetch_access, int hit_latency)
             : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
-              blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
-              prefetcher(_prefetcher), prefetchAccess(prefetch_access)
+              blockOnCopy(false), baseParams(params),
+              prefetcher(_prefetcher), prefetchAccess(prefetch_access),
+              hitLatency(hit_latency)
         {
         }
     };
 
     /** Instantiates a basic cache object. */
-    Cache(const std::string &_name, HierParams *hier_params, Params &params);
+    Cache(const std::string &_name, Params &params);
+
+    virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+                        bool isCpuSide);
+
+    virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
+
+    virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
+
+    virtual void recvStatusChange(Port::Status status, bool isCpuSide);
 
     void regStats();
 
@@ -147,13 +162,13 @@ class Cache : public BaseCache
      * @param req The request to perform.
      * @return The result of the access.
      */
-    MemAccessResult access(Packet * &pkt);
+    bool access(Packet * &pkt);
 
     /**
      * Selects a request to send on the bus.
      * @return The memory request to service.
      */
-    Packet * getPacket();
+    virtual Packet * getPacket();
 
     /**
      * Was the request was sent successfully?
@@ -226,16 +241,6 @@ class Cache : public BaseCache
         return missQueue->getMisses();
     }
 
-    /**
-     * Send a response to the slave interface.
-     * @param req The request being responded to.
-     * @param time The time the response is ready.
-     */
-    void respond(Packet * &pkt, Tick time)
-    {
-        si->respond(pkt,time);
-    }
-
     /**
      * Perform the access specified in the request and return the estimated
      * time of completion. This function can either update the hierarchy state