/*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
/**
* @file
- * Describes a cache based on template policies.
+ * Describes a cache
*/
#ifndef __MEM_CACHE_CACHE_HH__
#define __MEM_CACHE_CACHE_HH__
-#include "base/misc.hh" // fatal, panic, and warn
+#include <cstdint>
+#include <unordered_set>
+
+#include "base/types.hh"
#include "mem/cache/base.hh"
-#include "mem/cache/blk.hh"
-#include "mem/cache/mshr.hh"
-#include "mem/cache/tags/base.hh"
-#include "params/Cache.hh"
-#include "sim/eventq.hh"
+#include "mem/packet.hh"
-//Forward decleration
-class BasePrefetcher;
+class CacheBlk;
+struct CacheParams;
+class MSHR;
/**
- * A template-policy based cache. The behavior of the cache can be altered by
- * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
+ * A coherent cache that can be arranged in flexible topologies.
*/
class Cache : public BaseCache
{
- public:
-
- /** A typedef for a list of CacheBlk pointers. */
- typedef std::list<CacheBlk*> BlkList;
-
protected:
-
- /**
- * The CPU-side port extends the base cache slave port with access
- * functions for functional, atomic and timing requests.
- */
- class CpuSidePort : public CacheSlavePort
- {
- private:
-
- // a pointer to our specific cache implementation
- Cache *cache;
-
- protected:
-
- virtual bool recvTimingSnoopResp(PacketPtr pkt);
-
- virtual bool recvTimingReq(PacketPtr pkt);
-
- virtual Tick recvAtomic(PacketPtr pkt);
-
- virtual void recvFunctional(PacketPtr pkt);
-
- virtual AddrRangeList getAddrRanges() const;
-
- public:
-
- CpuSidePort(const std::string &_name, Cache *_cache,
- const std::string &_label);
-
- };
-
/**
- * Override the default behaviour of sendDeferredPacket to enable
- * the memory-side cache port to also send requests based on the
- * current MSHR status. This queue has a pointer to our specific
- * cache implementation and is used by the MemSidePort.
- */
- class CacheReqPacketQueue : public ReqPacketQueue
- {
-
- protected:
-
- Cache &cache;
- SnoopRespPacketQueue &snoopRespQueue;
-
- public:
-
- CacheReqPacketQueue(Cache &cache, MasterPort &port,
- SnoopRespPacketQueue &snoop_resp_queue,
- const std::string &label) :
- ReqPacketQueue(cache, port, label), cache(cache),
- snoopRespQueue(snoop_resp_queue) { }
-
- /**
- * Override the normal sendDeferredPacket and do not only
- * consider the transmit list (used for responses), but also
- * requests.
- */
- virtual void sendDeferredPacket();
-
- };
-
- /**
- * The memory-side port extends the base cache master port with
- * access functions for functional, atomic and timing snoops.
+ * This cache should allocate a block on a line-sized write miss.
*/
- class MemSidePort : public CacheMasterPort
- {
- private:
-
- /** The cache-specific queue. */
- CacheReqPacketQueue _reqQueue;
-
- SnoopRespPacketQueue _snoopRespQueue;
-
- // a pointer to our specific cache implementation
- Cache *cache;
-
- protected:
-
- virtual void recvTimingSnoopReq(PacketPtr pkt);
-
- virtual bool recvTimingResp(PacketPtr pkt);
-
- virtual Tick recvAtomicSnoop(PacketPtr pkt);
-
- virtual void recvFunctionalSnoop(PacketPtr pkt);
-
- public:
-
- MemSidePort(const std::string &_name, Cache *_cache,
- const std::string &_label);
- };
-
- /** Tag and data Storage */
- BaseTags *tags;
-
- /** Prefetcher */
- BasePrefetcher *prefetcher;
-
- /** Temporary cache block for occasional transitory use */
- CacheBlk *tempBlock;
+ const bool doFastWrites;
/**
- * This cache should allocate a block on a line-sized write miss.
+ * Store the outstanding requests that we are expecting snoop
+ * responses from so we can determine which snoop responses we
+ * generated and which ones were merely forwarded.
*/
- const bool doFastWrites;
+ std::unordered_set<RequestPtr> outstandingSnoop;
+ protected:
/**
* Turn line-sized writes into WriteInvalidate transactions.
*/
void promoteWholeLineWrites(PacketPtr pkt);
- /**
- * Notify the prefetcher on every access, not just misses.
- */
- const bool prefetchOnAccess;
+ bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
+ PacketList &writebacks) override;
- /**
- * @todo this is a temporary workaround until the 4-phase code is committed.
- * upstream caches need this packet until true is returned, so hold it for
- * deletion until a subsequent call
- */
- std::vector<PacketPtr> pendingDelete;
+ void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
+ Tick request_time) override;
- /**
- * Does all the processing necessary to perform the provided request.
- * @param pkt The memory request to perform.
- * @param blk The cache block to be updated.
- * @param lat The latency of the access.
- * @param writebacks List for any writebacks that need to be performed.
- * @return Boolean indicating whether the request was satisfied.
- */
- bool access(PacketPtr pkt, CacheBlk *&blk,
- Cycles &lat, PacketList &writebacks);
+ void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
+ Tick forward_time,
+ Tick request_time) override;
- /**
- *Handle doing the Compare and Swap function for SPARC.
- */
- void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
+ void recvTimingReq(PacketPtr pkt) override;
- /**
- * Find a block frame for new block at address addr targeting the
- * given security space, assuming that the block is not currently
- * in the cache. Append writebacks if any to provided packet
- * list. Return free block frame. May return NULL if there are
- * no replaceable blocks at the moment.
- */
- CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
+ void doWritebacks(PacketList& writebacks, Tick forward_time) override;
- /**
- * Populates a cache block and handles all outstanding requests for the
- * satisfied fill request. This version takes two memory requests. One
- * contains the fill data, the other is an optional target to satisfy.
- * @param pkt The memory request with the fill data.
- * @param blk The cache block if it already exists.
- * @param writebacks List for any writebacks that need to be performed.
- * @return Pointer to the new cache block.
- */
- CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
- PacketList &writebacks);
+ void doWritebacksAtomic(PacketList& writebacks) override;
+ void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
+ CacheBlk *blk) override;
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
- */
- bool recvTimingReq(PacketPtr pkt);
+ void recvTimingSnoopReq(PacketPtr pkt) override;
- /**
- * Insert writebacks into the write buffer
- */
- void doWritebacks(PacketList& writebacks, Tick forward_time);
+ void recvTimingSnoopResp(PacketPtr pkt) override;
- /**
- * Send writebacks down the memory hierarchy in atomic mode
- */
- void doWritebacksAtomic(PacketList& writebacks);
+ Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
+ PacketList &writebacks) override;
- /**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The response packet
- */
- void recvTimingResp(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt) override;
- /**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
- */
- void recvTimingSnoopReq(PacketPtr pkt);
+ Tick recvAtomicSnoop(PacketPtr pkt) override;
- /**
- * Handle a snoop response.
- * @param pkt Snoop response packet
- */
- void recvTimingSnoopResp(PacketPtr pkt);
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The number of ticks required for the access.
- */
- Tick recvAtomic(PacketPtr pkt);
-
- /**
- * Snoop for the provided request in the cache and return the estimated
- * time taken.
- * @param pkt The memory request to snoop
- * @return The number of ticks required for the snoop.
- */
- Tick recvAtomicSnoop(PacketPtr pkt);
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @param fromCpuSide from the CPU side port or the memory side port
- */
- void functionalAccess(PacketPtr pkt, bool fromCpuSide);
-
- void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
- bool deferred_response = false,
- bool pending_downgrade = false);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
+ void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false) override;
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
bool already_copied, bool pending_inval);
uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
bool is_timing, bool is_deferred, bool pending_inval);
- /**
- * Create a writeback request for the given block.
- * @param blk The block to writeback.
- * @return The writeback request for the block.
- */
- PacketPtr writebackBlk(CacheBlk *blk);
+ M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
/**
* Create a CleanEvict request for the given block.
+ *
* @param blk The block to evict.
* @return The CleanEvict request for the block.
*/
PacketPtr cleanEvictBlk(CacheBlk *blk);
-
- void memWriteback();
- void memInvalidate();
- bool isDirty() const;
-
- /**
- * Cache block visitor that writes back dirty cache blocks using
- * functional writes.
- *
- * \return Always returns true.
- */
- bool writebackVisitor(CacheBlk &blk);
- /**
- * Cache block visitor that invalidates all blocks in the cache.
- *
- * @warn Dirty cache lines will not be written back to memory.
- *
- * \return Always returns true.
- */
- bool invalidateVisitor(CacheBlk &blk);
-
- /**
- * Generate an appropriate downstream bus request packet for the
- * given parameters.
- * @param cpu_pkt The upstream request that needs to be satisfied.
- * @param blk The block currently in the cache corresponding to
- * cpu_pkt (NULL if none).
- * @param needsExclusive Indicates that an exclusive copy is required
- * even if the request in cpu_pkt doesn't indicate that.
- * @return A new Packet containing the request, or NULL if the
- * current request in cpu_pkt should just be forwarded on.
- */
- PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
- bool needsExclusive) const;
-
- /**
- * Return the next MSHR to service, either a pending miss from the
- * mshrQueue, a buffered write from the write buffer, or something
- * from the prefetcher. This function is responsible for
- * prioritizing among those sources on the fly.
- */
- MSHR *getNextMSHR();
+ PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
+ bool needs_writable,
+ bool is_whole_line_write) const override;
/**
* Send up a snoop request and find cached copies. If cached copies are
* found, set the BLOCK_CACHED flag in pkt.
*/
- bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const;
-
- /**
- * Selects an outstanding request to service. Called when the
- * cache gets granted the downstream bus in timing mode.
- * @return The request to service, NULL if none found.
- */
- PacketPtr getTimingPacket();
-
- /**
- * Marks a request as in service (sent on the bus). This can have
- * side effect since storage for no response commands is
- * deallocated once they are successfully sent. Also remember if
- * we are expecting a dirty response from another cache,
- * effectively making this MSHR the ordering point.
- */
- void markInService(MSHR *mshr, bool pending_dirty_resp);
-
- /**
- * Return whether there are any outstanding misses.
- */
- bool outstandingMisses() const
- {
- return mshrQueue.allocated != 0;
- }
-
- CacheBlk *findBlock(Addr addr, bool is_secure) const {
- return tags->findBlock(addr, is_secure);
- }
-
- bool inCache(Addr addr, bool is_secure) const {
- return (tags->findBlock(addr, is_secure) != 0);
- }
-
- bool inMissQueue(Addr addr, bool is_secure) const {
- return (mshrQueue.findMatch(addr, is_secure) != 0);
- }
-
- /**
- * Find next request ready time from among possible sources.
- */
- Tick nextMSHRReadyTime() const;
+ bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
public:
/** Instantiates a basic cache object. */
Cache(const CacheParams *p);
- /** Non-default destructor is needed to deallocate memory. */
- virtual ~Cache();
-
- void regStats();
-
- /** serialize the state of the caches
- * We currently don't support checkpointing cache state, so this panics.
- */
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-};
-
-/**
- * Wrap a method and present it as a cache block visitor.
- *
- * For example the forEachBlk method in the tag arrays expects a
- * callable object/function as their parameter. This class wraps a
- * method in an object and presents callable object that adheres to
- * the cache block visitor protocol.
- */
-class CacheBlkVisitorWrapper : public CacheBlkVisitor
-{
- public:
- typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
-
- CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
- : cache(_cache), visitor(_visitor) {}
-
- bool operator()(CacheBlk &blk) override {
- return (cache.*visitor)(blk);
- }
-
- private:
- Cache &cache;
- VisitorPtr visitor;
-};
-
-/**
- * Cache block visitor that determines if there are dirty blocks in a
- * cache.
- *
- * Use with the forEachBlk method in the tag array to determine if the
- * array contains dirty blocks.
- */
-class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
-{
- public:
- CacheBlkIsDirtyVisitor()
- : _isDirty(false) {}
-
- bool operator()(CacheBlk &blk) override {
- if (blk.isDirty()) {
- _isDirty = true;
- return false;
- } else {
- return true;
- }
- }
-
/**
- * Does the array contain a dirty line?
+ * Take an MSHR, turn it into a suitable downstream packet, and
+ * send it out. This construct allows a queue entry to choose a suitable
+ * approach based on its type.
*
- * \return true if yes, false otherwise.
+ * @param mshr The MSHR to turn into a packet and send
+ * @return True if the port is waiting for a retry
*/
- bool isDirty() const { return _isDirty; };
-
- private:
- bool _isDirty;
+ bool sendMSHRQueuePacket(MSHR* mshr) override;
};
#endif // __MEM_CACHE_CACHE_HH__
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