Fix problems with unCacheable addresses in timing-coherence

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 923bf825534889e3dfeb9b9f8a26e53b2710048e..41b270030b73684148ea5dc6b635fd05c975ae1f 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -103,6 +103,7 @@ class Cache : public BaseCache
       * Used to append to target list, to cause an invalidation.
       */
     Packet * invalidatePkt;
+    Request *invalidateReq;
 
     /**
      * Temporarily move a block into a MSHR.