Fix CSHR retrys

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1243c9d9ecd151000cfe61fddfa03586e20dafb1..41b270030b73684148ea5dc6b635fd05c975ae1f 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -103,12 +103,13 @@ class Cache : public BaseCache
       * Used to append to target list, to cause an invalidation.
       */
     Packet * invalidatePkt;
+    Request *invalidateReq;
 
     /**
      * Temporarily move a block into a MSHR.
      * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
      */
-    void pseudoFill(Addr addr, int asid);
+    void pseudoFill(Addr addr);
 
     /**
      * Temporarily move a block into an existing MSHR.
@@ -159,7 +160,7 @@ class Cache : public BaseCache
 
     /**
      * Performs the access specified by the request.
-     * @param req The request to perform.
+     * @param pkt The request to perform.
      * @return The result of the access.
      */
     bool access(Packet * &pkt);
@@ -168,30 +169,30 @@ class Cache : public BaseCache
      * Selects a request to send on the bus.
      * @return The memory request to service.
      */
-    Packet * getPacket();
+    virtual Packet * getPacket();
 
     /**
      * Was the request was sent successfully?
-     * @param req The request.
+     * @param pkt The request.
      * @param success True if the request was sent successfully.
      */
-    void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.
-     * @param req The request being responded to.
+     * @param pkt The request being responded to.
      */
     void handleResponse(Packet * &pkt);
 
     /**
      * Start handling a copy transaction.
-     * @param req The copy request to perform.
+     * @param pkt The copy request to perform.
      */
     void startCopy(Packet * &pkt);
 
     /**
      * Handle a delayed copy transaction.
-     * @param req The delayed copy request to continue.
+     * @param pkt The delayed copy request to continue.
      * @param addr The address being responded to.
      * @param blk The block of the current response.
      * @param mshr The mshr being handled.
@@ -202,11 +203,11 @@ class Cache : public BaseCache
      * Selects a coherence message to forward to lower levels of the hierarchy.
      * @return The coherence message to forward.
      */
-    Packet * getCoherenceReq();
+    virtual Packet * getCoherencePacket();
 
     /**
      * Snoops bus transactions to maintain coherence.
-     * @param req The current bus transaction.
+     * @param pkt The current bus transaction.
      */
     void snoop(Packet * &pkt);
 
@@ -218,12 +219,12 @@ class Cache : public BaseCache
      * @param asid The address space ID of the address.
      * @todo Is this function necessary?
      */
-    void invalidateBlk(Addr addr, int asid);
+    void invalidateBlk(Addr addr);
 
     /**
-     * Aquash all requests associated with specified thread.
+     * Squash all requests associated with specified thread.
      * intended for use by I-cache.
-     * @param req->getThreadNum()ber The thread to squash.
+     * @param threadNum The thread to squash.
      */
     void squash(int threadNum)
     {
@@ -241,39 +242,28 @@ class Cache : public BaseCache
         return missQueue->getMisses();
     }
 
-    /**
-     * Send a response to the slave interface.
-     * @param req The request being responded to.
-     * @param time The time the response is ready.
-     */
-    void respond(Packet * &pkt, Tick time)
-    {
-        //si->respond(pkt,time);
-        cpuSidePort->sendAtomic(pkt);
-    }
-
     /**
      * Perform the access specified in the request and return the estimated
      * time of completion. This function can either update the hierarchy state
      * or just perform the access wherever the data is found depending on the
      * state of the update flag.
-     * @param req The memory request to satisfy
+     * @param pkt The memory request to satisfy
      * @param update If true, update the hierarchy, otherwise just perform the
      * request.
      * @return The estimated completion time.
      */
-    Tick probe(Packet * &pkt, bool update);
+    Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
 
     /**
      * Snoop for the provided request in the cache and return the estimated
      * time of completion.
      * @todo Can a snoop probe not change state?
-     * @param req The memory request to satisfy
+     * @param pkt The memory request to satisfy
      * @param update If true, update the hierarchy, otherwise just perform the
      * request.
      * @return The estimated completion time.
      */
-    Tick snoopProbe(Packet * &pkt, bool update);
+    Tick snoopProbe(Packet * &pkt);
 };
 
 #endif // __CACHE_HH__