/*
+ * Copyright (c) 2012-2014 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Dave Greene
* Steve Reinhardt
* Ron Dreslinski
+ * Andreas Hansson
*/
/**
#ifndef __CACHE_HH__
#define __CACHE_HH__
-#include "base/compression/base.hh"
#include "base/misc.hh" // fatal, panic, and warn
-#include "cpu/smt.hh" // SMT_MAX_THREADS
-
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/mshr.hh"
-
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
+#include "mem/cache/tags/base.hh"
#include "sim/eventq.hh"
//Forward decleration
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
- * @sa MissQueue. Coherence handles all coherence policy details @sa
- * UniCoherence, SimpleMultiCoherence.
+ * storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
*/
-template <class TagStore, class Coherence>
class Cache : public BaseCache
{
public:
- /** Define the type of cache block to use. */
- typedef typename TagStore::BlkType BlkType;
- /** A typedef for a list of BlkType pointers. */
- typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
+ /** A typedef for a list of CacheBlk pointers. */
+ typedef std::list<CacheBlk*> BlkList;
protected:
- class CpuSidePort : public CachePort
+ /**
+ * The CPU-side port extends the base cache slave port with access
+ * functions for functional, atomic and timing requests.
+ */
+ class CpuSidePort : public CacheSlavePort
{
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
-
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
- }
+ private:
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
+ // a pointer to our specific cache implementation
+ Cache *cache;
- virtual bool recvTiming(PacketPtr pkt);
+ protected:
+
+ virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+ virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ virtual AddrRangeList getAddrRanges() const;
+
+ public:
+
+ CpuSidePort(const std::string &_name, Cache *_cache,
+ const std::string &_label);
+
};
- class MemSidePort : public CachePort
+ /**
+ * Override the default behaviour of sendDeferredPacket to enable
+ * the memory-side cache port to also send requests based on the
+ * current MSHR status. This queue has a pointer to our specific
+ * cache implementation and is used by the MemSidePort.
+ */
+ class CacheReqPacketQueue : public ReqPacketQueue
{
+
+ protected:
+
+ Cache &cache;
+ SnoopRespPacketQueue &snoopRespQueue;
+
public:
- MemSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
-
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
- }
- void sendPacket();
+ CacheReqPacketQueue(Cache &cache, MasterPort &port,
+ SnoopRespPacketQueue &snoop_resp_queue,
+ const std::string &label) :
+ ReqPacketQueue(cache, port, label), cache(cache),
+ snoopRespQueue(snoop_resp_queue) { }
- void processSendEvent();
+ /**
+ * Override the normal sendDeferredPacket and do not only
+ * consider the transmit list (used for responses), but also
+ * requests.
+ */
+ virtual void sendDeferredPacket();
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
+ };
- virtual bool recvTiming(PacketPtr pkt);
+ /**
+ * The memory-side port extends the base cache master port with
+ * access functions for functional, atomic and timing snoops.
+ */
+ class MemSidePort : public CacheMasterPort
+ {
+ private:
- virtual void recvRetry();
+ /** The cache-specific queue. */
+ CacheReqPacketQueue _reqQueue;
- virtual Tick recvAtomic(PacketPtr pkt);
+ SnoopRespPacketQueue _snoopRespQueue;
- virtual void recvFunctional(PacketPtr pkt);
+ // a pointer to our specific cache implementation
+ Cache *cache;
+
+ protected:
+
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
+ virtual bool recvTimingResp(PacketPtr pkt);
+
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
- typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
- SendEvent;
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+
+ public:
+
+ MemSidePort(const std::string &_name, Cache *_cache,
+ const std::string &_label);
};
/** Tag and data Storage */
- TagStore *tags;
-
- /** Coherence protocol. */
- Coherence *coherence;
+ BaseTags *tags;
/** Prefetcher */
BasePrefetcher *prefetcher;
+ /** Temporary cache block for occasional transitory use */
+ CacheBlk *tempBlock;
+
/**
- * The clock ratio of the outgoing bus.
- * Used for calculating critical word first.
+ * This cache should allocate a block on a line-sized write miss.
*/
- int busRatio;
-
- /**
- * The bus width in bytes of the outgoing bus.
- * Used for calculating critical word first.
- */
- int busWidth;
+ const bool doFastWrites;
/**
- * The latency of a hit in this device.
+ * Turn line-sized writes into WriteInvalidate transactions.
*/
- int hitLatency;
+ void promoteWholeLineWrites(PacketPtr pkt);
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * Notify the prefetcher on every access, not just misses.
*/
- const bool doFastWrites;
-
- const bool prefetchMiss;
+ const bool prefetchOnAccess;
/**
- * Handle a replacement for the given request.
- * @param blk A pointer to the block, usually NULL
- * @param pkt The memory request to satisfy.
- * @param new_state The new state of the block.
- * @param writebacks A list to store any generated writebacks.
+ * @todo this is a temporary workaround until the 4-phase code is committed.
+ * upstream caches need this packet until true is returned, so hold it for
+ * deletion until a subsequent call
*/
- BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
- CacheBlk::State new_state, PacketList &writebacks);
+ std::vector<PacketPtr> pendingDelete;
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
+ * @param blk The cache block to be updated.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
- * @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
- bool access(PacketPtr pkt, BlkType *&blk, int &lat);
+ bool access(PacketPtr pkt, CacheBlk *&blk,
+ Cycles &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
*/
- void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+ void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
+
+ /**
+ * Find a block frame for new block at address addr targeting the
+ * given security space, assuming that the block is not currently
+ * in the cache. Append writebacks if any to provided packet
+ * list. Return free block frame. May return NULL if there are
+ * no replaceable blocks at the moment.
+ */
+ CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
* satisfied fill request. This version takes two memory requests. One
* contains the fill data, the other is an optional target to satisfy.
- * Used for Cache::probe.
* @param pkt The memory request with the fill data.
* @param blk The cache block if it already exists.
* @param writebacks List for any writebacks that need to be performed.
* @return Pointer to the new cache block.
*/
- BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks);
- bool satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
- bool satisfyTarget(MSHR::Target *target, BlkType *blk);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
-
- void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data);
/**
- * Sets the blk to the new state.
- * @param blk The cache block being snooped.
- * @param new_state The new coherence state for the block.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- void handleSnoop(PacketPtr ptk, BlkType *blk, bool is_timing);
+ bool recvTimingReq(PacketPtr pkt);
/**
- * Create a writeback request for the given block.
- * @param blk The block to writeback.
- * @return The writeback request for the block.
+ * Insert writebacks into the write buffer
*/
- PacketPtr writebackBlk(BlkType *blk);
+ void doWritebacks(PacketList& writebacks, Tick forward_time);
- public:
-
- class Params
- {
- public:
- TagStore *tags;
- Coherence *coherence;
- BaseCache::Params baseParams;
- BasePrefetcher*prefetcher;
- bool prefetchAccess;
- const bool doFastWrites;
- const bool prefetchMiss;
-
- Params(TagStore *_tags, Coherence *coh,
- BaseCache::Params params,
- BasePrefetcher *_prefetcher,
- bool prefetch_access, int hit_latency,
- bool do_fast_writes,
- bool prefetch_miss)
- : tags(_tags), coherence(coh),
- baseParams(params),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- doFastWrites(do_fast_writes),
- prefetchMiss(prefetch_miss)
- {
- }
- };
-
- /** Instantiates a basic cache object. */
- Cache(const std::string &_name, Params ¶ms);
+ /**
+ * Handles a response (cache line fill/write ack) from the bus.
+ * @param pkt The response packet
+ */
+ void recvTimingResp(PacketPtr pkt);
- virtual Port *getPort(const std::string &if_name, int idx = -1);
- virtual void deletePortRefs(Port *p);
+ /**
+ * Snoops bus transactions to maintain coherence.
+ * @param pkt The current bus transaction.
+ */
+ void recvTimingSnoopReq(PacketPtr pkt);
- void regStats();
+ /**
+ * Handle a snoop response.
+ * @param pkt Snoop response packet
+ */
+ void recvTimingSnoopResp(PacketPtr pkt);
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @return The number of ticks required for the access.
*/
- bool timingAccess(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt);
/**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
+ * Snoop for the provided request in the cache and return the estimated
+ * time taken.
+ * @param pkt The memory request to snoop
+ * @return The number of ticks required for the snoop.
*/
- Tick atomicAccess(PacketPtr pkt);
+ Tick recvAtomicSnoop(PacketPtr pkt);
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @param fromCpuSide from the CPU side port or the memory side port
*/
- void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
+ void functionalAccess(PacketPtr pkt, bool fromCpuSide);
+
+ void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
+
+ void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
+ bool already_copied, bool pending_inval);
/**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The request being responded to.
+ * Sets the blk to the new state.
+ * @param blk The cache block being snooped.
+ * @param new_state The new coherence state for the block.
*/
- void handleResponse(PacketPtr pkt);
+ void handleSnoop(PacketPtr ptk, CacheBlk *blk,
+ bool is_timing, bool is_deferred, bool pending_inval);
/**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
+ * Create a writeback request for the given block.
+ * @param blk The block to writeback.
+ * @return The writeback request for the block.
*/
- void snoopTiming(PacketPtr pkt);
+ PacketPtr writebackBlk(CacheBlk *blk);
/**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @param pkt The memory request to snoop
- * @return The estimated completion time.
+ * Create a CleanEvict request for the given block.
+ * @param blk The block to evict.
+ * @return The CleanEvict request for the block.
*/
- Tick snoopAtomic(PacketPtr pkt);
+ PacketPtr cleanEvictBlk(CacheBlk *blk);
+
+
+ void memWriteback();
+ void memInvalidate();
+ bool isDirty() const;
+
+ /**
+ * Cache block visitor that writes back dirty cache blocks using
+ * functional writes.
+ *
+ * \return Always returns true.
+ */
+ bool writebackVisitor(CacheBlk &blk);
+ /**
+ * Cache block visitor that invalidates all blocks in the cache.
+ *
+ * @warn Dirty cache lines will not be written back to memory.
+ *
+ * \return Always returns true.
+ */
+ bool invalidateVisitor(CacheBlk &blk);
/**
* Squash all requests associated with specified thread.
void squash(int threadNum);
/**
- * Allocate a new MSHR or write buffer to handle a miss.
- * @param pkt The access that missed.
- * @param time The time to continue processing the miss.
- * @param isFill Whether to fetch & allocate a block
- * or just forward the request.
+ * Generate an appropriate downstream bus request packet for the
+ * given parameters.
+ * @param cpu_pkt The upstream request that needs to be satisfied.
+ * @param blk The block currently in the cache corresponding to
+ * cpu_pkt (NULL if none).
+ * @param needsExclusive Indicates that an exclusive copy is required
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @return A new Packet containing the request, or NULL if the
+ * current request in cpu_pkt should just be forwarded on.
*/
- MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus);
+ PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
+ bool needsExclusive) const;
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Return the next MSHR to service, either a pending miss from the
+ * mshrQueue, a buffered write from the write buffer, or something
+ * from the prefetcher. This function is responsible for
+ * prioritizing among those sources on the fly.
*/
- PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive);
MSHR *getNextMSHR();
- PacketPtr getTimingPacket();
/**
- * Marks a request as in service (sent on the bus). This can have side
- * effect since storage for no response commands is deallocated once they
- * are successfully sent.
- * @param pkt The request that was sent on the bus.
+ * Send up a snoop request and find cached copies. If cached copies are
+ * found, set the BLOCK_CACHED flag in pkt.
+ */
+ bool isCachedAbove(const PacketPtr pkt) const;
+
+ /**
+ * Selects an outstanding request to service. Called when the
+ * cache gets granted the downstream bus in timing mode.
+ * @return The request to service, NULL if none found.
*/
- void markInService(MSHR *mshr);
+ PacketPtr getTimingPacket();
/**
- * Perform the given writeback request.
- * @param pkt The writeback request.
+ * Marks a request as in service (sent on the bus). This can have
+ * side effect since storage for no response commands is
+ * deallocated once they are successfully sent. Also remember if
+ * we are expecting a dirty response from another cache,
+ * effectively making this MSHR the ordering point.
*/
- void doWriteback(PacketPtr pkt);
+ void markInService(MSHR *mshr, bool pending_dirty_resp);
/**
* Return whether there are any outstanding misses.
return mshrQueue.allocated != 0;
}
- CacheBlk *findBlock(Addr addr) {
- return tags->findBlock(addr);
+ CacheBlk *findBlock(Addr addr, bool is_secure) const {
+ return tags->findBlock(addr, is_secure);
}
- bool inCache(Addr addr) {
- return (tags->findBlock(addr) != 0);
+ bool inCache(Addr addr, bool is_secure) const {
+ return (tags->findBlock(addr, is_secure) != 0);
}
- bool inMissQueue(Addr addr) {
- return (mshrQueue.findMatch(addr) != 0);
+ bool inMissQueue(Addr addr, bool is_secure) const {
+ return (mshrQueue.findMatch(addr, is_secure) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime() const;
+
+ public:
+ /** Instantiates a basic cache object. */
+ Cache(const Params *p);
+
+ /** Non-default destructor is needed to deallocate memory. */
+ virtual ~Cache();
+
+ void regStats();
+
+ /** serialize the state of the caches
+ * We currently don't support checkpointing cache state, so this panics.
+ */
+ virtual void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+};
+
+/**
+ * Wrap a method and present it as a cache block visitor.
+ *
+ * For example the forEachBlk method in the tag arrays expects a
+ * callable object/function as their parameter. This class wraps a
+ * method in an object and presents callable object that adheres to
+ * the cache block visitor protocol.
+ */
+class CacheBlkVisitorWrapper : public CacheBlkVisitor
+{
+ public:
+ typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
+
+ CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
+ : cache(_cache), visitor(_visitor) {}
+
+ bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ return (cache.*visitor)(blk);
+ }
+
+ private:
+ Cache &cache;
+ VisitorPtr visitor;
+};
+
+/**
+ * Cache block visitor that determines if there are dirty blocks in a
+ * cache.
+ *
+ * Use with the forEachBlk method in the tag array to determine if the
+ * array contains dirty blocks.
+ */
+class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
+{
+ public:
+ CacheBlkIsDirtyVisitor()
+ : _isDirty(false) {}
+
+ bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ if (blk.isDirty()) {
+ _isDirty = true;
+ return false;
+ } else {
+ return true;
+ }
+ }
+
+ /**
+ * Does the array contain a dirty line?
+ *
+ * \return true if yes, false otherwise.
+ */
+ bool isDirty() const { return _isDirty; };
+
+ private:
+ bool _isDirty;
};
#endif // __CACHE_HH__
projects / gem5.git / blobdiff