#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
+#include "mem/cache/tags/base.hh"
#include "sim/eventq.hh"
//Forward decleration
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
*/
-template <class TagStore>
class Cache : public BaseCache
{
public:
- /** Define the type of cache block to use. */
- typedef typename TagStore::BlkType BlkType;
- /** A typedef for a list of BlkType pointers. */
- typedef typename TagStore::BlkList BlkList;
+
+ /** A typedef for a list of CacheBlk pointers. */
+ typedef std::list<CacheBlk*> BlkList;
protected:
- typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
/**
* The CPU-side port extends the base cache slave port with access
private:
// a pointer to our specific cache implementation
- Cache<TagStore> *cache;
+ Cache *cache;
protected:
public:
- CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ CpuSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
protected:
- Cache<TagStore> &cache;
+ Cache &cache;
SnoopRespPacketQueue &snoopRespQueue;
public:
- CacheReqPacketQueue(Cache<TagStore> &cache, MasterPort &port,
+ CacheReqPacketQueue(Cache &cache, MasterPort &port,
SnoopRespPacketQueue &snoop_resp_queue,
const std::string &label) :
ReqPacketQueue(cache, port, label), cache(cache),
SnoopRespPacketQueue _snoopRespQueue;
// a pointer to our specific cache implementation
- Cache<TagStore> *cache;
+ Cache *cache;
protected:
public:
- MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ MemSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
/** Tag and data Storage */
- TagStore *tags;
+ BaseTags *tags;
/** Prefetcher */
BasePrefetcher *prefetcher;
/** Temporary cache block for occasional transitory use */
- BlkType *tempBlock;
+ CacheBlk *tempBlock;
/**
* This cache should allocate a block on a line-sized write miss.
* @param writebacks List for any writebacks that need to be performed.
* @return Boolean indicating whether the request was satisfied.
*/
- bool access(PacketPtr pkt, BlkType *&blk,
+ bool access(PacketPtr pkt, CacheBlk *&blk,
Cycles &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
*/
- void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+ void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
/**
* Find a block frame for new block at address addr targeting the
* list. Return free block frame. May return NULL if there are
* no replaceable blocks at the moment.
*/
- BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
+ CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
* @param writebacks List for any writebacks that need to be performed.
* @return Pointer to the new cache block.
*/
- BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks);
*/
bool recvTimingReq(PacketPtr pkt);
+ /**
+ * Insert writebacks into the write buffer
+ */
+ void doWritebacks(PacketList& writebacks, Tick forward_time);
+
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The response packet
*/
void functionalAccess(PacketPtr pkt, bool fromCpuSide);
- void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
+ void satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
bool deferred_response = false,
bool pending_downgrade = false);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, CacheBlk *blk);
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
bool already_copied, bool pending_inval);
* @param blk The cache block being snooped.
* @param new_state The new coherence state for the block.
*/
- void handleSnoop(PacketPtr ptk, BlkType *blk,
+ void handleSnoop(PacketPtr ptk, CacheBlk *blk,
bool is_timing, bool is_deferred, bool pending_inval);
/**
* @param blk The block to writeback.
* @return The writeback request for the block.
*/
- PacketPtr writebackBlk(BlkType *blk);
+ PacketPtr writebackBlk(CacheBlk *blk);
+
+ /**
+ * Create a CleanEvict request for the given block.
+ * @param blk The block to evict.
+ * @return The CleanEvict request for the block.
+ */
+ PacketPtr cleanEvictBlk(CacheBlk *blk);
void memWriteback();
*
* \return Always returns true.
*/
- bool writebackVisitor(BlkType &blk);
+ bool writebackVisitor(CacheBlk &blk);
/**
* Cache block visitor that invalidates all blocks in the cache.
*
*
* \return Always returns true.
*/
- bool invalidateVisitor(BlkType &blk);
-
- /**
- * Flush a cache line due to an uncacheable memory access to the
- * line.
- *
- * @note This shouldn't normally happen, but we need to handle it
- * since some architecture models don't implement cache
- * maintenance operations. We won't even try to get a decent
- * timing here since the line should have been flushed earlier by
- * a cache maintenance operation.
- */
- void uncacheableFlush(PacketPtr pkt);
+ bool invalidateVisitor(CacheBlk &blk);
/**
* Squash all requests associated with specified thread.
* @return A new Packet containing the request, or NULL if the
* current request in cpu_pkt should just be forwarded on.
*/
- PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
+ PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
bool needsExclusive) const;
/**
*/
MSHR *getNextMSHR();
+ /**
+ * Send up a snoop request and find cached copies. If cached copies are
+ * found, set the BLOCK_CACHED flag in pkt.
+ */
+ bool isCachedAbove(const PacketPtr pkt) const;
+
/**
* Selects an outstanding request to service. Called when the
* cache gets granted the downstream bus in timing mode.
void unserialize(Checkpoint *cp, const std::string §ion);
};
+/**
+ * Wrap a method and present it as a cache block visitor.
+ *
+ * For example the forEachBlk method in the tag arrays expects a
+ * callable object/function as their parameter. This class wraps a
+ * method in an object and presents callable object that adheres to
+ * the cache block visitor protocol.
+ */
+class CacheBlkVisitorWrapper : public CacheBlkVisitor
+{
+ public:
+ typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
+
+ CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
+ : cache(_cache), visitor(_visitor) {}
+
+ bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ return (cache.*visitor)(blk);
+ }
+
+ private:
+ Cache &cache;
+ VisitorPtr visitor;
+};
+
+/**
+ * Cache block visitor that determines if there are dirty blocks in a
+ * cache.
+ *
+ * Use with the forEachBlk method in the tag array to determine if the
+ * array contains dirty blocks.
+ */
+class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
+{
+ public:
+ CacheBlkIsDirtyVisitor()
+ : _isDirty(false) {}
+
+ bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE {
+ if (blk.isDirty()) {
+ _isDirty = true;
+ return false;
+ } else {
+ return true;
+ }
+ }
+
+ /**
+ * Does the array contain a dirty line?
+ *
+ * \return true if yes, false otherwise.
+ */
+ bool isDirty() const { return _isDirty; };
+
+ private:
+ bool _isDirty;
+};
+
#endif // __CACHE_HH__
projects / gem5.git / blobdiff