* Authors: Erik Hallnor
* Dave Greene
* Steve Reinhardt
+ * Ron Dreslinski
*/
/**
#define __CACHE_HH__
#include "base/misc.hh" // fatal, panic, and warn
-#include "cpu/smt.hh" // SMT_MAX_THREADS
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/miss/miss_buffer.hh"
-#include "mem/cache/prefetch/prefetcher.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
-//Forward decleration
-class MSHR;
+#include "sim/eventq.hh"
+//Forward decleration
+class BasePrefetcher;
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
- * @sa MissQueue. Coherence handles all coherence policy details @sa
- * UniCoherence, SimpleMultiCoherence.
+ * storage @sa TagStore.
*/
-template <class TagStore, class Coherence>
+template <class TagStore>
class Cache : public BaseCache
{
public:
/** Define the type of cache block to use. */
typedef typename TagStore::BlkType BlkType;
-
- bool prefetchAccess;
+ /** A typedef for a list of BlkType pointers. */
+ typedef typename TagStore::BlkList BlkList;
protected:
{
public:
CpuSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
+ Cache<TagStore> *_cache,
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
// cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
+ Cache<TagStore> *myCache() {
+ return static_cast<Cache<TagStore> *>(cache);
}
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
{
public:
MemSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
+ Cache<TagStore> *_cache,
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
// cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
+ Cache<TagStore> *myCache() {
+ return static_cast<Cache<TagStore> *>(cache);
}
+ void sendPacket();
+
+ void processSendEvent();
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop);
+
virtual bool recvTiming(PacketPtr pkt);
+ virtual void recvRetry();
+
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
+ SendEvent;
};
/** Tag and data Storage */
TagStore *tags;
- /** Miss and Writeback handler */
- MissBuffer *missQueue;
- /** Coherence protocol. */
- Coherence *coherence;
/** Prefetcher */
- Prefetcher<TagStore> *prefetcher;
+ BasePrefetcher *prefetcher;
+
+ /** Temporary cache block for occasional transitory use */
+ BlkType *tempBlock;
/**
- * The clock ratio of the outgoing bus.
- * Used for calculating critical word first.
+ * This cache should allocate a block on a line-sized write miss.
*/
- int busRatio;
+ const bool doFastWrites;
- /**
- * The bus width in bytes of the outgoing bus.
- * Used for calculating critical word first.
- */
- int busWidth;
+ /**
+ * Notify the prefetcher on every access, not just misses.
+ */
+ const bool prefetchOnAccess;
/**
- * The latency of a hit in this device.
+ * Does all the processing necessary to perform the provided request.
+ * @param pkt The memory request to perform.
+ * @param lat The latency of the access.
+ * @param writebacks List for any writebacks that need to be performed.
+ * @param update True if the replacement data should be updated.
+ * @return Boolean indicating whether the request was satisfied.
*/
- int hitLatency;
+ bool access(PacketPtr pkt, BlkType *&blk,
+ int &lat, PacketList &writebacks);
- /**
- * A permanent mem req to always be used to cause invalidations.
- * Used to append to target list, to cause an invalidation.
- */
- PacketPtr invalidatePkt;
- Request *invalidateReq;
+ /**
+ *Handle doing the Compare and Swap function for SPARC.
+ */
+ void cmpAndSwap(BlkType *blk, PacketPtr pkt);
- public:
+ /**
+ * Find a block frame for new block at address addr, assuming that
+ * the block is not currently in the cache. Append writebacks if
+ * any to provided packet list. Return free block frame. May
+ * return NULL if there are no replaceable blocks at the moment.
+ */
+ BlkType *allocateBlock(Addr addr, PacketList &writebacks);
- class Params
- {
- public:
- TagStore *tags;
- MissBuffer *missQueue;
- Coherence *coherence;
- BaseCache::Params baseParams;
- Prefetcher<TagStore> *prefetcher;
- bool prefetchAccess;
- int hitLatency;
-
- Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
- BaseCache::Params params,
- Prefetcher<TagStore> *_prefetcher,
- bool prefetch_access, int hit_latency)
- : tags(_tags), missQueue(mq), coherence(coh),
- baseParams(params),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- hitLatency(hit_latency)
- {
- }
- };
+ /**
+ * Populates a cache block and handles all outstanding requests for the
+ * satisfied fill request. This version takes two memory requests. One
+ * contains the fill data, the other is an optional target to satisfy.
+ * @param pkt The memory request with the fill data.
+ * @param blk The cache block if it already exists.
+ * @param writebacks List for any writebacks that need to be performed.
+ * @return Pointer to the new cache block.
+ */
+ BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ PacketList &writebacks);
+
+ void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+
+ void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
+ bool already_copied, bool pending_inval);
+ /**
+ * Sets the blk to the new state.
+ * @param blk The cache block being snooped.
+ * @param new_state The new coherence state for the block.
+ */
+ void handleSnoop(PacketPtr ptk, BlkType *blk,
+ bool is_timing, bool is_deferred, bool pending_inval);
+
+ /**
+ * Create a writeback request for the given block.
+ * @param blk The block to writeback.
+ * @return The writeback request for the block.
+ */
+ PacketPtr writebackBlk(BlkType *blk);
+
+ public:
/** Instantiates a basic cache object. */
- Cache(const std::string &_name, Params ¶ms);
+ Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
virtual Port *getPort(const std::string &if_name, int idx = -1);
-
- virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+ virtual void deletePortRefs(Port *p);
void regStats();
* @param pkt The request to perform.
* @return The result of the access.
*/
- bool access(PacketPtr &pkt);
+ bool timingAccess(PacketPtr pkt);
/**
- * Selects a request to send on the bus.
- * @return The memory request to service.
- */
- virtual PacketPtr getPacket();
-
- /**
- * Was the request was sent successfully?
- * @param pkt The request.
- * @param success True if the request was sent successfully.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
+ Tick atomicAccess(PacketPtr pkt);
/**
- * Was the CSHR request was sent successfully?
- * @param pkt The request.
- * @param success True if the request was sent successfully.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
+ void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
+ CachePort *otherSidePort);
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The request being responded to.
*/
- void handleResponse(PacketPtr &pkt);
-
- /**
- * Selects a coherence message to forward to lower levels of the hierarchy.
- * @return The coherence message to forward.
- */
- virtual PacketPtr getCoherencePacket();
+ void handleResponse(PacketPtr pkt);
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
- void snoop(PacketPtr &pkt);
-
- void snoopResponse(PacketPtr &pkt);
+ void snoopTiming(PacketPtr pkt);
/**
- * Invalidates the block containing address if found.
- * @param addr The address to look for.
- * @param asid The address space ID of the address.
- * @todo Is this function necessary?
+ * Snoop for the provided request in the cache and return the estimated
+ * time of completion.
+ * @param pkt The memory request to snoop
+ * @return The estimated completion time.
*/
- void invalidateBlk(Addr addr);
+ Tick snoopAtomic(PacketPtr pkt);
/**
* Squash all requests associated with specified thread.
* intended for use by I-cache.
* @param threadNum The thread to squash.
*/
- void squash(int threadNum)
- {
- missQueue->squash(threadNum);
- }
+ void squash(int threadNum);
/**
- * Return the number of outstanding misses in a Cache.
- * Default returns 0.
- *
- * @retval unsigned The number of missing still outstanding.
+ * Generate an appropriate downstream bus request packet for the
+ * given parameters.
+ * @param cpu_pkt The upstream request that needs to be satisfied.
+ * @param blk The block currently in the cache corresponding to
+ * cpu_pkt (NULL if none).
+ * @param needsExclusive Indicates that an exclusive copy is required
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @return A new Packet containing the request, or NULL if the
+ * current request in cpu_pkt should just be forwarded on.
*/
- unsigned outstandingMisses() const
- {
- return missQueue->getMisses();
- }
+ PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
+ bool needsExclusive);
/**
- * Perform the access specified in the request and return the estimated
- * time of completion. This function can either update the hierarchy state
- * or just perform the access wherever the data is found depending on the
- * state of the update flag.
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
+ * Return the next MSHR to service, either a pending miss from the
+ * mshrQueue, a buffered write from the write buffer, or something
+ * from the prefetcher. This function is responsible for
+ * prioritizing among those sources on the fly.
*/
- Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
+ MSHR *getNextMSHR();
/**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @todo Can a snoop probe not change state?
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
+ * Selects an outstanding request to service. Called when the
+ * cache gets granted the downstream bus in timing mode.
+ * @return The request to service, NULL if none found.
+ */
+ PacketPtr getTimingPacket();
+
+ /**
+ * Marks a request as in service (sent on the bus). This can have side
+ * effect since storage for no response commands is deallocated once they
+ * are successfully sent.
+ * @param pkt The request that was sent on the bus.
+ */
+ void markInService(MSHR *mshr);
+
+ /**
+ * Perform the given writeback request.
+ * @param pkt The writeback request.
+ */
+ void doWriteback(PacketPtr pkt);
+
+ /**
+ * Return whether there are any outstanding misses.
+ */
+ bool outstandingMisses() const
+ {
+ return mshrQueue.allocated != 0;
+ }
+
+ CacheBlk *findBlock(Addr addr) {
+ return tags->findBlock(addr);
+ }
+
+ bool inCache(Addr addr) {
+ return (tags->findBlock(addr) != 0);
+ }
+
+ bool inMissQueue(Addr addr) {
+ return (mshrQueue.findMatch(addr) != 0);
+ }
+
+ /**
+ * Find next request ready time from among possible sources.
*/
- Tick snoopProbe(PacketPtr &pkt);
+ Tick nextMSHRReadyTime();
};
#endif // __CACHE_HH__
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