/** A typedef for a list of BlkType pointers. */
typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
-
protected:
class CpuSidePort : public CachePort
public:
CpuSidePort(const std::string &_name,
Cache<TagStore> *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filterRanges);
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
public:
MemSidePort(const std::string &_name,
Cache<TagStore> *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filterRanges);
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
BlkType *tempBlock;
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
- const bool prefetchMiss;
+ /**
+ * Notify the prefetcher on every access, not just misses.
+ */
+ const bool prefetchOnAccess;
/**
* Does all the processing necessary to perform the provided request.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks);
bool inMissQueue(Addr addr) {
return (mshrQueue.findMatch(addr) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime();
};
#endif // __CACHE_HH__