#include "base/misc.hh" // fatal, panic, and warn
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/mshr.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
#include "sim/eventq.hh"
/** A typedef for a list of BlkType pointers. */
typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
-
protected:
class CpuSidePort : public CachePort
{
public:
CpuSidePort(const std::string &_name,
- Cache<TagStore> *_cache);
+ Cache<TagStore> *_cache,
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
{
public:
MemSidePort(const std::string &_name,
- Cache<TagStore> *_cache);
+ Cache<TagStore> *_cache,
+ const std::string &_label);
// BaseCache::CachePort just has a BaseCache *; this function
// lets us get back the type info we lost when we stored the
BlkType *tempBlock;
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
- const bool prefetchMiss;
-
/**
- * Handle a replacement for the given request.
- * @param blk A pointer to the block, usually NULL
- * @param pkt The memory request to satisfy.
- * @param new_state The new state of the block.
- * @param writebacks A list to store any generated writebacks.
+ * Notify the prefetcher on every access, not just misses.
*/
- BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
- CacheBlk::State new_state, PacketList &writebacks);
+ const bool prefetchOnAccess;
/**
* Does all the processing necessary to perform the provided request.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
- bool access(PacketPtr pkt, BlkType *&blk, int &lat);
+ bool access(PacketPtr pkt, BlkType *&blk,
+ int &lat, PacketList &writebacks);
/**
*Handle doing the Compare and Swap function for SPARC.
*/
void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+ /**
+ * Find a block frame for new block at address addr, assuming that
+ * the block is not currently in the cache. Append writebacks if
+ * any to provided packet list. Return free block frame. May
+ * return NULL if there are no replaceable blocks at the moment.
+ */
+ BlkType *allocateBlock(Addr addr, PacketList &writebacks);
+
/**
* Populates a cache block and handles all outstanding requests for the
* satisfied fill request. This version takes two memory requests. One
* contains the fill data, the other is an optional target to satisfy.
- * Used for Cache::probe.
* @param pkt The memory request with the fill data.
* @param blk The cache block if it already exists.
* @param writebacks List for any writebacks that need to be performed.
bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
- bool already_copied);
+ bool already_copied, bool pending_inval);
/**
* Sets the blk to the new state.
* @param new_state The new coherence state for the block.
*/
void handleSnoop(PacketPtr ptk, BlkType *blk,
- bool is_timing, bool is_deferred);
+ bool is_timing, bool is_deferred, bool pending_inval);
/**
* Create a writeback request for the given block.
PacketPtr writebackBlk(BlkType *blk);
public:
-
- class Params
- {
- public:
- TagStore *tags;
- BaseCache::Params baseParams;
- BasePrefetcher*prefetcher;
- bool prefetchAccess;
- const bool doFastWrites;
- const bool prefetchMiss;
-
- Params(TagStore *_tags,
- BaseCache::Params params,
- BasePrefetcher *_prefetcher,
- bool prefetch_access, int hit_latency,
- bool do_fast_writes,
- bool prefetch_miss)
- : tags(_tags),
- baseParams(params),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- doFastWrites(do_fast_writes),
- prefetchMiss(prefetch_miss)
- {
- }
- };
-
/** Instantiates a basic cache object. */
- Cache(const std::string &_name, Params ¶ms);
+ Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
virtual Port *getPort(const std::string &if_name, int idx = -1);
virtual void deletePortRefs(Port *p);
* @param pkt The request to perform.
* @return The result of the access.
*/
- void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
+ void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
+ CachePort *otherSidePort);
/**
* Handles a response (cache line fill/write ack) from the bus.
void squash(int threadNum);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Generate an appropriate downstream bus request packet for the
+ * given parameters.
+ * @param cpu_pkt The upstream request that needs to be satisfied.
+ * @param blk The block currently in the cache corresponding to
+ * cpu_pkt (NULL if none).
+ * @param needsExclusive Indicates that an exclusive copy is required
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @return A new Packet containing the request, or NULL if the
+ * current request in cpu_pkt should just be forwarded on.
*/
PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
bool needsExclusive);
+
+ /**
+ * Return the next MSHR to service, either a pending miss from the
+ * mshrQueue, a buffered write from the write buffer, or something
+ * from the prefetcher. This function is responsible for
+ * prioritizing among those sources on the fly.
+ */
MSHR *getNextMSHR();
+
+ /**
+ * Selects an outstanding request to service. Called when the
+ * cache gets granted the downstream bus in timing mode.
+ * @return The request to service, NULL if none found.
+ */
PacketPtr getTimingPacket();
/**
bool inMissQueue(Addr addr) {
return (mshrQueue.findMatch(addr) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime();
};
#endif // __CACHE_HH__
projects / gem5.git / blobdiff