Include packet_impl.hh (need this on my laptop,

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 4b8870c959b2a6ca028148d91ba28a2b87a6554b..7024ce58ac4b8f50215e8929c7fd2c8b47eefb12 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -103,6 +103,7 @@ class Cache : public BaseCache
       * Used to append to target list, to cause an invalidation.
       */
     Packet * invalidatePkt;
+    Request *invalidateReq;
 
     /**
      * Temporarily move a block into a MSHR.
@@ -175,7 +176,14 @@ class Cache : public BaseCache
      * @param pkt The request.
      * @param success True if the request was sent successfully.
      */
-    virtual void sendResult(Packet * &pkt, bool success);
+    virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
+
+    /**
+     * Was the CSHR request was sent successfully?
+     * @param pkt The request.
+     * @param success True if the request was sent successfully.
+     */
+    virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
 
     /**
      * Handles a response (cache line fill/write ack) from the bus.