#include "mem/cache/base_cache.hh"
#include "mem/cache/prefetch/prefetcher.hh"
-// forward declarations
-class Bus;
-class ExecContext;
+//Forward decleration
+class MSHR;
+
/**
* A template-policy based cache. The behavior of the cache can be altered by
*/
int busWidth;
+ /**
+ * The latency of a hit in this device.
+ */
+ int hitLatency;
+
/**
* A permanent mem req to always be used to cause invalidations.
* Used to append to target list, to cause an invalidation.
*/
Packet * invalidatePkt;
+ Request *invalidateReq;
/**
* Temporarily move a block into a MSHR.
* @todo Remove this when LSQ/SB are fixed and implemented in memtest.
*/
- void pseudoFill(Addr addr, int asid);
+ void pseudoFill(Addr addr);
/**
* Temporarily move a block into an existing MSHR.
bool doCopy;
bool blockOnCopy;
BaseCache::Params baseParams;
- Bus *in;
- Bus *out;
Prefetcher<TagStore, Buffering> *prefetcher;
bool prefetchAccess;
+ int hitLatency;
Params(TagStore *_tags, Buffering *mq, Coherence *coh,
- bool do_copy, BaseCache::Params params, Bus * in_bus,
- Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
- bool prefetch_access)
+ bool do_copy, BaseCache::Params params,
+ Prefetcher<TagStore, Buffering> *_prefetcher,
+ bool prefetch_access, int hit_latency)
: tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
- blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access)
+ blockOnCopy(false), baseParams(params),
+ prefetcher(_prefetcher), prefetchAccess(prefetch_access),
+ hitLatency(hit_latency)
{
}
};
/** Instantiates a basic cache object. */
- Cache(const std::string &_name, HierParams *hier_params, Params ¶ms);
+ Cache(const std::string &_name, Params ¶ms);
+
+ virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+ bool isCpuSide);
+
+ virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
+
+ virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
+
+ virtual void recvStatusChange(Port::Status status, bool isCpuSide);
void regStats();
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
- MemAccessResult access(Packet * &pkt);
+ bool access(Packet * &pkt);
/**
* Selects a request to send on the bus.
* @return The memory request to service.
*/
- Packet * getPacket();
+ virtual Packet * getPacket();
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
- void sendResult(Packet * &pkt, bool success);
+ virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success);
+
+ /**
+ * Was the CSHR request was sent successfully?
+ * @param pkt The request.
+ * @param success True if the request was sent successfully.
+ */
+ virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
/**
* Start handling a copy transaction.
- * @param req The copy request to perform.
+ * @param pkt The copy request to perform.
*/
void startCopy(Packet * &pkt);
/**
* Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
+ * @param pkt The delayed copy request to continue.
* @param addr The address being responded to.
* @param blk The block of the current response.
* @param mshr The mshr being handled.
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
- Packet * getCoherenceReq();
+ virtual Packet * getCoherencePacket();
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
* @param asid The address space ID of the address.
* @todo Is this function necessary?
*/
- void invalidateBlk(Addr addr, int asid);
+ void invalidateBlk(Addr addr);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param thread_number The thread to squash.
+ * @param threadNum The thread to squash.
*/
- void squash(int thread_number)
+ void squash(int threadNum)
{
- missQueue->squash(thread_number);
+ missQueue->squash(threadNum);
}
/**
return missQueue->getMisses();
}
- /**
- * Send a response to the slave interface.
- * @param req The request being responded to.
- * @param time The time the response is ready.
- */
- void respond(Packet * &pkt, Tick time)
- {
- si->respond(pkt,time);
- }
-
/**
* Perform the access specified in the request and return the estimated
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
*/
- Tick probe(Packet * &pkt, bool update);
+ Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
*/
- Tick snoopProbe(Packet * &pkt, bool update);
+ Tick snoopProbe(Packet * &pkt);
};
#endif // __CACHE_HH__
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