/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Authors: Erik Hallnor
* Dave Greene
* Steve Reinhardt
+ * Ron Dreslinski
+ * Andreas Hansson
*/
/**
#ifndef __CACHE_HH__
#define __CACHE_HH__
-#include "base/compression/base.hh"
#include "base/misc.hh" // fatal, panic, and warn
-#include "cpu/smt.hh" // SMT_MAX_THREADS
-
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/miss_buffer.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
+#include "sim/eventq.hh"
//Forward decleration
-class MSHR;
class BasePrefetcher;
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
- * @sa MissQueue. Coherence handles all coherence policy details @sa
- * UniCoherence, SimpleMultiCoherence.
+ * storage @sa TagStore.
*/
-template <class TagStore, class Coherence>
+template <class TagStore>
class Cache : public BaseCache
{
public:
/** A typedef for a list of BlkType pointers. */
typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
-
protected:
- class CpuSidePort : public CachePort
+ /**
+ * The CPU-side port extends the base cache slave port with access
+ * functions for functional, atomic and timing requests.
+ */
+ class CpuSidePort : public CacheSlavePort
{
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
+ private:
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
- }
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual bool recvTiming(PacketPtr pkt);
+ protected:
+
+ virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+ virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ virtual unsigned deviceBlockSize() const
+ { return cache->getBlockSize(); }
+
+ virtual AddrRangeList getAddrRanges() const;
+
+ public:
+
+ CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
+
};
- class MemSidePort : public CachePort
+ /**
+ * Override the default behaviour of sendDeferredPacket to enable
+ * the memory-side cache port to also send requests based on the
+ * current MSHR status. This queue has a pointer to our specific
+ * cache implementation and is used by the MemSidePort.
+ */
+ class MemSidePacketQueue : public MasterPacketQueue
{
- public:
- MemSidePort(const std::string &_name,
- Cache<TagStore,Coherence> *_cache);
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore,Coherence> *myCache() {
- return static_cast<Cache<TagStore,Coherence> *>(cache);
- }
+ protected:
- virtual bool recvTiming(PacketPtr pkt);
+ Cache<TagStore> &cache;
- virtual Tick recvAtomic(PacketPtr pkt);
+ public:
- virtual void recvFunctional(PacketPtr pkt);
- };
+ MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
+ const std::string &label) :
+ MasterPacketQueue(cache, port, label), cache(cache) { }
- /** Tag and data Storage */
- TagStore *tags;
- /** Miss and Writeback handler */
- MissBuffer *missQueue;
- /** Coherence protocol. */
- Coherence *coherence;
+ /**
+ * Override the normal sendDeferredPacket and do not only
+ * consider the transmit list (used for responses), but also
+ * requests.
+ */
+ virtual void sendDeferredPacket();
- /** Prefetcher */
- BasePrefetcher *prefetcher;
+ };
/**
- * The clock ratio of the outgoing bus.
- * Used for calculating critical word first.
+ * The memory-side port extends the base cache master port with
+ * access functions for functional, atomic and timing snoops.
*/
- int busRatio;
+ class MemSidePort : public CacheMasterPort
+ {
+ private:
- /**
- * The bus width in bytes of the outgoing bus.
- * Used for calculating critical word first.
- */
- int busWidth;
+ /** The cache-specific queue. */
+ MemSidePacketQueue _queue;
- /**
- * The latency of a hit in this device.
- */
- int hitLatency;
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- /**
- * A permanent mem req to always be used to cause invalidations.
- * Used to append to target list, to cause an invalidation.
- */
- PacketPtr invalidatePkt;
- Request *invalidateReq;
+ protected:
- /**
- * Policy class for performing compression.
- */
- CompressionAlgorithm *compressionAlg;
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
- /**
- * The block size of this cache. Set to value in the Tags object.
- */
- const int16_t blkSize;
+ virtual bool recvTimingResp(PacketPtr pkt);
- /**
- * Can this cache should allocate a block on a line-sized write miss.
- */
- const bool doFastWrites;
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
- const bool prefetchMiss;
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
- /**
- * Can the data can be stored in a compressed form.
- */
- const bool storeCompressed;
+ virtual unsigned deviceBlockSize() const
+ { return cache->getBlockSize(); }
- /**
- * Do we need to compress blocks on writebacks (i.e. because
- * writeback bus is compressed but storage is not)?
- */
- const bool compressOnWriteback;
+ public:
- /**
- * The latency of a compression operation.
- */
- const int16_t compLatency;
+ MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
+ };
- /**
- * Should we use an adaptive compression scheme.
- */
- const bool adaptiveCompression;
+ /** Tag and data Storage */
+ TagStore *tags;
- /**
- * Do writebacks need to be compressed (i.e. because writeback bus
- * is compressed), whether or not they're already compressed for
- * storage.
- */
- const bool writebackCompressed;
+ /** Prefetcher */
+ BasePrefetcher *prefetcher;
+
+ /** Temporary cache block for occasional transitory use */
+ BlkType *tempBlock;
/**
- * Compare the internal block data to the fast access block data.
- * @param blk The cache block to check.
- * @return True if the data is the same.
+ * This cache should allocate a block on a line-sized write miss.
*/
- bool verifyData(BlkType *blk);
+ const bool doFastWrites;
/**
- * Update the internal data of the block. The data to write is assumed to
- * be in the fast access data.
- * @param blk The block with the data to update.
- * @param writebacks A list to store any generated writebacks.
- * @param compress_block True if we should compress this block
+ * Notify the prefetcher on every access, not just misses.
*/
- void updateData(BlkType *blk, PacketList &writebacks, bool compress_block);
+ const bool prefetchOnAccess;
/**
- * Handle a replacement for the given request.
- * @param blk A pointer to the block, usually NULL
- * @param pkt The memory request to satisfy.
- * @param new_state The new state of the block.
- * @param writebacks A list to store any generated writebacks.
+ * @todo this is a temporary workaround until the 4-phase code is committed.
+ * upstream caches need this packet until true is returned, so hold it for
+ * deletion until a subsequent call
*/
- BlkType* doReplacement(BlkType *blk, PacketPtr &pkt,
- CacheBlk::State new_state, PacketList &writebacks);
+ std::vector<PacketPtr> pendingDelete;
/**
* Does all the processing necessary to perform the provided request.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
- BlkType* handleAccess(PacketPtr &pkt, int & lat,
- PacketList & writebacks, bool update = true);
+ bool access(PacketPtr pkt, BlkType *&blk,
+ int &lat, PacketList &writebacks);
/**
- * Populates a cache block and handles all outstanding requests for the
- * satisfied fill request. This version takes an MSHR pointer and uses its
- * request to fill the cache block, while repsonding to its targets.
- * @param blk The cache block if it already exists.
- * @param mshr The MSHR that contains the fill data and targets to satisfy.
- * @param new_state The state of the new cache block.
- * @param writebacks List for any writebacks that need to be performed.
- * @return Pointer to the new cache block.
+ *Handle doing the Compare and Swap function for SPARC.
+ */
+ void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+
+ /**
+ * Find a block frame for new block at address addr, assuming that
+ * the block is not currently in the cache. Append writebacks if
+ * any to provided packet list. Return free block frame. May
+ * return NULL if there are no replaceable blocks at the moment.
*/
- BlkType* handleFill(BlkType *blk, MSHR * mshr, CacheBlk::State new_state,
- PacketList & writebacks, PacketPtr pkt);
+ BlkType *allocateBlock(Addr addr, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
* satisfied fill request. This version takes two memory requests. One
* contains the fill data, the other is an optional target to satisfy.
- * Used for Cache::probe.
- * @param blk The cache block if it already exists.
* @param pkt The memory request with the fill data.
- * @param new_state The state of the new cache block.
+ * @param blk The cache block if it already exists.
* @param writebacks List for any writebacks that need to be performed.
- * @param target The memory request to perform after the fill.
* @return Pointer to the new cache block.
*/
- BlkType* handleFill(BlkType *blk, PacketPtr &pkt,
- CacheBlk::State new_state,
- PacketList & writebacks, PacketPtr target = NULL);
+ BlkType *handleFill(PacketPtr pkt, BlkType *blk,
+ PacketList &writebacks);
- /**
- * Sets the blk to the new state and handles the given request.
- * @param blk The cache block being snooped.
- * @param new_state The new coherence state for the block.
- * @param pkt The request to satisfy
- */
- void handleSnoop(BlkType *blk, CacheBlk::State new_state,
- PacketPtr &pkt);
+ void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false);
+ bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+
+ void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
+ bool already_copied, bool pending_inval);
/**
* Sets the blk to the new state.
* @param blk The cache block being snooped.
* @param new_state The new coherence state for the block.
*/
- void handleSnoop(BlkType *blk, CacheBlk::State new_state);
+ void handleSnoop(PacketPtr ptk, BlkType *blk,
+ bool is_timing, bool is_deferred, bool pending_inval);
/**
* Create a writeback request for the given block.
PacketPtr writebackBlk(BlkType *blk);
public:
-
- class Params
- {
- public:
- TagStore *tags;
- MissBuffer *missQueue;
- Coherence *coherence;
- BaseCache::Params baseParams;
- BasePrefetcher*prefetcher;
- bool prefetchAccess;
- int hitLatency;
- CompressionAlgorithm *compressionAlg;
- const int16_t blkSize;
- const bool doFastWrites;
- const bool prefetchMiss;
- const bool storeCompressed;
- const bool compressOnWriteback;
- const int16_t compLatency;
- const bool adaptiveCompression;
- const bool writebackCompressed;
-
- Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
- BaseCache::Params params,
- BasePrefetcher *_prefetcher,
- bool prefetch_access, int hit_latency,
- bool do_fast_writes,
- bool store_compressed, bool adaptive_compression,
- bool writeback_compressed,
- CompressionAlgorithm *_compressionAlg, int comp_latency,
- bool prefetch_miss)
- : tags(_tags), missQueue(mq), coherence(coh),
- baseParams(params),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- hitLatency(hit_latency),
- compressionAlg(_compressionAlg),
- blkSize(_tags->getBlockSize()),
- doFastWrites(do_fast_writes),
- prefetchMiss(prefetch_miss),
- storeCompressed(store_compressed),
- compressOnWriteback(!store_compressed && writeback_compressed),
- compLatency(comp_latency),
- adaptiveCompression(adaptive_compression),
- writebackCompressed(writeback_compressed)
- {
- }
- };
-
/** Instantiates a basic cache object. */
- Cache(const std::string &_name, Params ¶ms);
-
- virtual Port *getPort(const std::string &if_name, int idx = -1);
-
- virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+ Cache(const Params *p, TagStore *tags);
void regStats();
* @param pkt The request to perform.
* @return The result of the access.
*/
- bool access(PacketPtr &pkt);
-
- /**
- * Selects a request to send on the bus.
- * @return The memory request to service.
- */
- virtual PacketPtr getPacket();
+ bool timingAccess(PacketPtr pkt);
/**
- * Was the request was sent successfully?
- * @param pkt The request.
- * @param success True if the request was sent successfully.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @return The result of the access.
*/
- virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
+ Tick atomicAccess(PacketPtr pkt);
/**
- * Was the CSHR request was sent successfully?
- * @param pkt The request.
- * @param success True if the request was sent successfully.
+ * Performs the access specified by the request.
+ * @param pkt The request to perform.
+ * @param fromCpuSide from the CPU side port or the memory side port
*/
- virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
+ void functionalAccess(PacketPtr pkt, bool fromCpuSide);
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The request being responded to.
*/
- void handleResponse(PacketPtr &pkt);
-
- /**
- * Selects a coherence message to forward to lower levels of the hierarchy.
- * @return The coherence message to forward.
- */
- virtual PacketPtr getCoherencePacket();
+ void handleResponse(PacketPtr pkt);
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
- void snoop(PacketPtr &pkt);
+ void snoopTiming(PacketPtr pkt);
- void snoopResponse(PacketPtr &pkt);
+ /**
+ * Snoop for the provided request in the cache and return the estimated
+ * time of completion.
+ * @param pkt The memory request to snoop
+ * @return The estimated completion time.
+ */
+ Tick snoopAtomic(PacketPtr pkt);
/**
* Squash all requests associated with specified thread.
* intended for use by I-cache.
* @param threadNum The thread to squash.
*/
- void squash(int threadNum)
- {
- missQueue->squash(threadNum);
- }
+ void squash(int threadNum);
/**
- * Return the number of outstanding misses in a Cache.
- * Default returns 0.
- *
- * @retval unsigned The number of missing still outstanding.
+ * Generate an appropriate downstream bus request packet for the
+ * given parameters.
+ * @param cpu_pkt The upstream request that needs to be satisfied.
+ * @param blk The block currently in the cache corresponding to
+ * cpu_pkt (NULL if none).
+ * @param needsExclusive Indicates that an exclusive copy is required
+ * even if the request in cpu_pkt doesn't indicate that.
+ * @return A new Packet containing the request, or NULL if the
+ * current request in cpu_pkt should just be forwarded on.
*/
- unsigned outstandingMisses() const
- {
- return missQueue->getMisses();
- }
+ PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
+ bool needsExclusive);
/**
- * Perform the access specified in the request and return the estimated
- * time of completion. This function can either update the hierarchy state
- * or just perform the access wherever the data is found depending on the
- * state of the update flag.
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
+ * Return the next MSHR to service, either a pending miss from the
+ * mshrQueue, a buffered write from the write buffer, or something
+ * from the prefetcher. This function is responsible for
+ * prioritizing among those sources on the fly.
*/
- Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
+ MSHR *getNextMSHR();
/**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @todo Can a snoop probe not change state?
- * @param pkt The memory request to satisfy
- * @param update If true, update the hierarchy, otherwise just perform the
- * request.
- * @return The estimated completion time.
+ * Selects an outstanding request to service. Called when the
+ * cache gets granted the downstream bus in timing mode.
+ * @return The request to service, NULL if none found.
*/
- Tick snoopProbe(PacketPtr &pkt);
+ PacketPtr getTimingPacket();
+
+ /**
+ * Marks a request as in service (sent on the bus). This can have side
+ * effect since storage for no response commands is deallocated once they
+ * are successfully sent.
+ * @param pkt The request that was sent on the bus.
+ */
+ void markInService(MSHR *mshr, PacketPtr pkt = 0);
+
+ /**
+ * Return whether there are any outstanding misses.
+ */
+ bool outstandingMisses() const
+ {
+ return mshrQueue.allocated != 0;
+ }
+
+ CacheBlk *findBlock(Addr addr) {
+ return tags->findBlock(addr);
+ }
bool inCache(Addr addr) {
return (tags->findBlock(addr) != 0);
}
bool inMissQueue(Addr addr) {
- return (missQueue->findMSHR(addr) != 0);
+ return (mshrQueue.findMatch(addr) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime();
+
+ /** serialize the state of the caches
+ * We currently don't support checkpointing cache state, so this panics.
+ */
+ virtual void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
#endif // __CACHE_HH__
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