Port: Make getAddrRanges const

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 2883955845d121272e45d7d28c5cb2d331b63997..9bdbd3456ab1356a530e792442a7f187bbad3140 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -90,7 +90,9 @@ class Cache : public BaseCache
 
       protected:
 
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+        virtual bool recvTimingReq(PacketPtr pkt);
 
         virtual Tick recvAtomic(PacketPtr pkt);
 
@@ -99,7 +101,7 @@ class Cache : public BaseCache
         virtual unsigned deviceBlockSize() const
         { return cache->getBlockSize(); }
 
-        virtual AddrRangeList getAddrRanges();
+        virtual AddrRangeList getAddrRanges() const;
 
       public:
 
@@ -108,6 +110,34 @@ class Cache : public BaseCache
 
     };
 
+    /**
+     * Override the default behaviour of sendDeferredPacket to enable
+     * the memory-side cache port to also send requests based on the
+     * current MSHR status. This queue has a pointer to our specific
+     * cache implementation and is used by the MemSidePort.
+     */
+    class MemSidePacketQueue : public MasterPacketQueue
+    {
+
+      protected:
+
+        Cache<TagStore> &cache;
+
+      public:
+
+        MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
+                           const std::string &label) :
+            MasterPacketQueue(cache, port, label), cache(cache) { }
+
+        /**
+         * Override the normal sendDeferredPacket and do not only
+         * consider the transmit list (used for responses), but also
+         * requests.
+         */
+        virtual void sendDeferredPacket();
+
+    };
+
     /**
      * The memory-side port extends the base cache master port with
      * access functions for functional, atomic and timing snoops.
@@ -116,16 +146,21 @@ class Cache : public BaseCache
     {
       private:
 
+        /** The cache-specific queue. */
+        MemSidePacketQueue _queue;
+
         // a pointer to our specific cache implementation
         Cache<TagStore> *cache;
 
       protected:
 
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual void recvTimingSnoopReq(PacketPtr pkt);
 
-        virtual Tick recvAtomic(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
 
-        virtual void recvFunctional(PacketPtr pkt);
+        virtual Tick recvAtomicSnoop(PacketPtr pkt);
+
+        virtual void recvFunctionalSnoop(PacketPtr pkt);
 
         virtual unsigned deviceBlockSize() const
         { return cache->getBlockSize(); }
@@ -134,11 +169,6 @@ class Cache : public BaseCache
 
         MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
                     const std::string &_label);
-
-        /**
-         * Overload sendDeferredPacket of SimpleTimingPort.
-         */
-        virtual void sendDeferredPacket();
     };
 
     /** Tag and data Storage */
@@ -160,6 +190,13 @@ class Cache : public BaseCache
      */
     const bool prefetchOnAccess;
 
+    /**
+     * @todo this is a temporary workaround until the 4-phase code is committed.
+     * upstream caches need this packet until true is returned, so hold it for
+     * deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
+
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.
@@ -223,8 +260,6 @@ class Cache : public BaseCache
     /** Instantiates a basic cache object. */
     Cache(const Params *p, TagStore *tags);
 
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
-
     void regStats();
 
     /**
@@ -312,12 +347,6 @@ class Cache : public BaseCache
      */
     void markInService(MSHR *mshr, PacketPtr pkt = 0);
 
-    /**
-     * Perform the given writeback request.
-     * @param pkt The writeback request.
-     */
-    void doWriteback(PacketPtr pkt);
-
     /**
      * Return whether there are any outstanding misses.
      */
@@ -342,6 +371,12 @@ class Cache : public BaseCache
      * Find next request ready time from among possible sources.
      */
     Tick nextMSHRReadyTime();
+
+    /** serialize the state of the caches
+     * We currently don't support checkpointing cache state, so this panics.
+     */
+    virtual void serialize(std::ostream &os);
+    void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 #endif // __CACHE_HH__