/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Dave Greene
* Steve Reinhardt
* Ron Dreslinski
+ * Andreas Hansson
*/
/**
#define __CACHE_HH__
#include "base/misc.hh" // fatal, panic, and warn
-
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
-
#include "sim/eventq.hh"
//Forward decleration
protected:
- class CpuSidePort : public CachePort
+ /**
+ * The CPU-side port extends the base cache slave port with access
+ * functions for functional, atomic and timing requests.
+ */
+ class CpuSidePort : public CacheSlavePort
{
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- const std::string &_label);
+ private:
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
+ protected:
- virtual bool recvTiming(PacketPtr pkt);
+ virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+ virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ virtual unsigned deviceBlockSize() const
+ { return cache->getBlockSize(); }
+
+ virtual AddrRangeList getAddrRanges() const;
+
+ public:
+
+ CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
+
};
- class MemSidePort : public CachePort
+ /**
+ * Override the default behaviour of sendDeferredPacket to enable
+ * the memory-side cache port to also send requests based on the
+ * current MSHR status. This queue has a pointer to our specific
+ * cache implementation and is used by the MemSidePort.
+ */
+ class MemSidePacketQueue : public MasterPacketQueue
{
+
+ protected:
+
+ Cache<TagStore> &cache;
+
public:
- MemSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- const std::string &_label);
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
+ MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
+ const std::string &label) :
+ MasterPacketQueue(cache, port, label), cache(cache) { }
- void sendPacket();
+ /**
+ * Override the normal sendDeferredPacket and do not only
+ * consider the transmit list (used for responses), but also
+ * requests.
+ */
+ virtual void sendDeferredPacket();
- void processSendEvent();
+ };
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
+ /**
+ * The memory-side port extends the base cache master port with
+ * access functions for functional, atomic and timing snoops.
+ */
+ class MemSidePort : public CacheMasterPort
+ {
+ private:
- virtual bool recvTiming(PacketPtr pkt);
+ /** The cache-specific queue. */
+ MemSidePacketQueue _queue;
- virtual void recvRetry();
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual Tick recvAtomic(PacketPtr pkt);
+ protected:
- virtual void recvFunctional(PacketPtr pkt);
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
+ virtual bool recvTimingResp(PacketPtr pkt);
+
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
+
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+
+ virtual unsigned deviceBlockSize() const
+ { return cache->getBlockSize(); }
+
+ public:
- typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
- SendEvent;
+ MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+ const std::string &_label);
};
/** Tag and data Storage */
*/
const bool prefetchOnAccess;
+ /**
+ * @todo this is a temporary workaround until the 4-phase code is committed.
+ * upstream caches need this packet until true is returned, so hold it for
+ * deletion until a subsequent call
+ */
+ std::vector<PacketPtr> pendingDelete;
+
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
BlkType *handleFill(PacketPtr pkt, BlkType *blk,
PacketList &writebacks);
- void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
+ void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false);
bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
public:
/** Instantiates a basic cache object. */
- Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
-
- virtual Port *getPort(const std::string &if_name, int idx = -1);
- virtual void deletePortRefs(Port *p);
+ Cache(const Params *p, TagStore *tags);
void regStats();
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @param fromCpuSide from the CPU side port or the memory side port
*/
- void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
- CachePort *otherSidePort);
+ void functionalAccess(PacketPtr pkt, bool fromCpuSide);
/**
* Handles a response (cache line fill/write ack) from the bus.
* are successfully sent.
* @param pkt The request that was sent on the bus.
*/
- void markInService(MSHR *mshr);
-
- /**
- * Perform the given writeback request.
- * @param pkt The writeback request.
- */
- void doWriteback(PacketPtr pkt);
+ void markInService(MSHR *mshr, PacketPtr pkt = 0);
/**
* Return whether there are any outstanding misses.
* Find next request ready time from among possible sources.
*/
Tick nextMSHRReadyTime();
+
+ /** serialize the state of the caches
+ * We currently don't support checkpointing cache state, so this panics.
+ */
+ virtual void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
#endif // __CACHE_HH__
projects / gem5.git / blobdiff