Port: Make getAddrRanges const

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index b5c95b301f89c907430c45e5b2f5c126cb0529cb..9bdbd3456ab1356a530e792442a7f187bbad3140 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -41,6 +41,7 @@
  *          Dave Greene
  *          Steve Reinhardt
  *          Ron Dreslinski
+ *          Andreas Hansson
  */
 
 /**
@@ -76,59 +77,98 @@ class Cache : public BaseCache
 
   protected:
 
-    class CpuSidePort : public CachePort
+    /**
+     * The CPU-side port extends the base cache slave port with access
+     * functions for functional, atomic and timing requests.
+     */
+    class CpuSidePort : public CacheSlavePort
     {
-      public:
-        CpuSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache,
-                    const std::string &_label);
+      private:
+
+        // a pointer to our specific cache implementation
+        Cache<TagStore> *cache;
 
-        // BaseCache::CachePort just has a BaseCache *; this function
-        // lets us get back the type info we lost when we stored the
-        // cache pointer there.
-        Cache<TagStore> *myCache() {
-            return static_cast<Cache<TagStore> *>(cache);
-        }
+      protected:
 
-        virtual AddrRangeList getAddrRanges();
+        virtual bool recvTimingSnoopResp(PacketPtr pkt);
 
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual bool recvTimingReq(PacketPtr pkt);
 
         virtual Tick recvAtomic(PacketPtr pkt);
 
         virtual void recvFunctional(PacketPtr pkt);
+
+        virtual unsigned deviceBlockSize() const
+        { return cache->getBlockSize(); }
+
+        virtual AddrRangeList getAddrRanges() const;
+
+      public:
+
+        CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
+                    const std::string &_label);
+
     };
 
-    class MemSidePort : public CachePort
+    /**
+     * Override the default behaviour of sendDeferredPacket to enable
+     * the memory-side cache port to also send requests based on the
+     * current MSHR status. This queue has a pointer to our specific
+     * cache implementation and is used by the MemSidePort.
+     */
+    class MemSidePacketQueue : public MasterPacketQueue
     {
+
+      protected:
+
+        Cache<TagStore> &cache;
+
       public:
-        MemSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache,
-                    const std::string &_label);
 
-        // BaseCache::CachePort just has a BaseCache *; this function
-        // lets us get back the type info we lost when we stored the
-        // cache pointer there.
-        Cache<TagStore> *myCache() {
-            return static_cast<Cache<TagStore> *>(cache);
-        }
+        MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
+                           const std::string &label) :
+            MasterPacketQueue(cache, port, label), cache(cache) { }
+
+        /**
+         * Override the normal sendDeferredPacket and do not only
+         * consider the transmit list (used for responses), but also
+         * requests.
+         */
+        virtual void sendDeferredPacket();
+
+    };
 
-        void sendPacket();
+    /**
+     * The memory-side port extends the base cache master port with
+     * access functions for functional, atomic and timing snoops.
+     */
+    class MemSidePort : public CacheMasterPort
+    {
+      private:
 
-        void processSendEvent();
+        /** The cache-specific queue. */
+        MemSidePacketQueue _queue;
 
-        virtual bool isSnooping();
+        // a pointer to our specific cache implementation
+        Cache<TagStore> *cache;
 
-        virtual bool recvTiming(PacketPtr pkt);
+      protected:
 
-        virtual void recvRetry();
+        virtual void recvTimingSnoopReq(PacketPtr pkt);
 
-        virtual Tick recvAtomic(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
 
-        virtual void recvFunctional(PacketPtr pkt);
+        virtual Tick recvAtomicSnoop(PacketPtr pkt);
+
+        virtual void recvFunctionalSnoop(PacketPtr pkt);
+
+        virtual unsigned deviceBlockSize() const
+        { return cache->getBlockSize(); }
+
+      public:
 
-        typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
-                SendEvent;
+        MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+                    const std::string &_label);
     };
 
     /** Tag and data Storage */
@@ -150,6 +190,13 @@ class Cache : public BaseCache
      */
     const bool prefetchOnAccess;
 
+    /**
+     * @todo this is a temporary workaround until the 4-phase code is committed.
+     * upstream caches need this packet until true is returned, so hold it for
+     * deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
+
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.
@@ -211,9 +258,7 @@ class Cache : public BaseCache
 
   public:
     /** Instantiates a basic cache object. */
-    Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
-
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    Cache(const Params *p, TagStore *tags);
 
     void regStats();
 
@@ -302,12 +347,6 @@ class Cache : public BaseCache
      */
     void markInService(MSHR *mshr, PacketPtr pkt = 0);
 
-    /**
-     * Perform the given writeback request.
-     * @param pkt The writeback request.
-     */
-    void doWriteback(PacketPtr pkt);
-
     /**
      * Return whether there are any outstanding misses.
      */
@@ -332,6 +371,12 @@ class Cache : public BaseCache
      * Find next request ready time from among possible sources.
      */
     Tick nextMSHRReadyTime();
+
+    /** serialize the state of the caches
+     * We currently don't support checkpointing cache state, so this panics.
+     */
+    virtual void serialize(std::ostream &os);
+    void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 #endif // __CACHE_HH__