Port: Make getAddrRanges const

[gem5.git] / src / mem / cache / cache.hh

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index e745529a75f4bb0f82a846e74b97fcbf49b1872a..9bdbd3456ab1356a530e792442a7f187bbad3140 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -90,7 +90,9 @@ class Cache : public BaseCache
 
       protected:
 
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual bool recvTimingSnoopResp(PacketPtr pkt);
+
+        virtual bool recvTimingReq(PacketPtr pkt);
 
         virtual Tick recvAtomic(PacketPtr pkt);
 
@@ -99,7 +101,7 @@ class Cache : public BaseCache
         virtual unsigned deviceBlockSize() const
         { return cache->getBlockSize(); }
 
-        virtual AddrRangeList getAddrRanges();
+        virtual AddrRangeList getAddrRanges() const;
 
       public:
 
@@ -114,7 +116,7 @@ class Cache : public BaseCache
      * current MSHR status. This queue has a pointer to our specific
      * cache implementation and is used by the MemSidePort.
      */
-    class MemSidePacketQueue : public PacketQueue
+    class MemSidePacketQueue : public MasterPacketQueue
     {
 
       protected:
@@ -123,9 +125,9 @@ class Cache : public BaseCache
 
       public:
 
-        MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
+        MemSidePacketQueue(Cache<TagStore> &cache, MasterPort &port,
                            const std::string &label) :
-            PacketQueue(cache, port, label), cache(cache) { }
+            MasterPacketQueue(cache, port, label), cache(cache) { }
 
         /**
          * Override the normal sendDeferredPacket and do not only
@@ -152,11 +154,13 @@ class Cache : public BaseCache
 
       protected:
 
-        virtual bool recvTiming(PacketPtr pkt);
+        virtual void recvTimingSnoopReq(PacketPtr pkt);
 
-        virtual Tick recvAtomic(PacketPtr pkt);
+        virtual bool recvTimingResp(PacketPtr pkt);
 
-        virtual void recvFunctional(PacketPtr pkt);
+        virtual Tick recvAtomicSnoop(PacketPtr pkt);
+
+        virtual void recvFunctionalSnoop(PacketPtr pkt);
 
         virtual unsigned deviceBlockSize() const
         { return cache->getBlockSize(); }
@@ -186,6 +190,13 @@ class Cache : public BaseCache
      */
     const bool prefetchOnAccess;
 
+    /**
+     * @todo this is a temporary workaround until the 4-phase code is committed.
+     * upstream caches need this packet until true is returned, so hold it for
+     * deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
+
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.
@@ -336,12 +347,6 @@ class Cache : public BaseCache
      */
     void markInService(MSHR *mshr, PacketPtr pkt = 0);
 
-    /**
-     * Perform the given writeback request.
-     * @param pkt The writeback request.
-     */
-    void doWriteback(PacketPtr pkt);
-
     /**
      * Return whether there are any outstanding misses.
      */
@@ -366,6 +371,12 @@ class Cache : public BaseCache
      * Find next request ready time from among possible sources.
      */
     Tick nextMSHRReadyTime();
+
+    /** serialize the state of the caches
+     * We currently don't support checkpointing cache state, so this panics.
+     */
+    virtual void serialize(std::ostream &os);
+    void unserialize(Checkpoint *cp, const std::string &section);
 };
 
 #endif // __CACHE_HH__