/*
+ * Copyright (c) 2012-2018 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Dave Greene
* Steve Reinhardt
* Ron Dreslinski
+ * Andreas Hansson
*/
/**
* @file
- * Describes a cache based on template policies.
+ * Describes a cache
*/
-#ifndef __CACHE_HH__
-#define __CACHE_HH__
-
-#include "base/misc.hh" // fatal, panic, and warn
+#ifndef __MEM_CACHE_CACHE_HH__
+#define __MEM_CACHE_CACHE_HH__
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/mshr.hh"
+#include <cstdint>
+#include <unordered_set>
-#include "sim/eventq.hh"
+#include "base/types.hh"
+#include "mem/cache/base.hh"
+#include "mem/packet.hh"
-//Forward decleration
-class BasePrefetcher;
+class CacheBlk;
+struct CacheParams;
+class MSHR;
/**
- * A template-policy based cache. The behavior of the cache can be altered by
- * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore.
+ * A coherent cache that can be arranged in flexible topologies.
*/
-template <class TagStore>
class Cache : public BaseCache
{
- public:
- /** Define the type of cache block to use. */
- typedef typename TagStore::BlkType BlkType;
- /** A typedef for a list of BlkType pointers. */
- typedef typename TagStore::BlkList BlkList;
-
- bool prefetchAccess;
-
protected:
-
- class CpuSidePort : public CachePort
- {
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- std::vector<Range<Addr> > filterRanges);
-
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
-
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
-
- virtual bool recvTiming(PacketPtr pkt);
-
- virtual Tick recvAtomic(PacketPtr pkt);
-
- virtual void recvFunctional(PacketPtr pkt);
- };
-
- class MemSidePort : public CachePort
- {
- public:
- MemSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- std::vector<Range<Addr> > filterRanges);
-
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
-
- void sendPacket();
-
- void processSendEvent();
-
- virtual void getDeviceAddressRanges(AddrRangeList &resp,
- bool &snoop);
-
- virtual bool recvTiming(PacketPtr pkt);
-
- virtual void recvRetry();
-
- virtual Tick recvAtomic(PacketPtr pkt);
-
- virtual void recvFunctional(PacketPtr pkt);
-
- typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
- SendEvent;
- };
-
- /** Tag and data Storage */
- TagStore *tags;
-
- /** Prefetcher */
- BasePrefetcher *prefetcher;
-
- /** Temporary cache block for occasional transitory use */
- BlkType *tempBlock;
-
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
- const bool prefetchMiss;
-
- /**
- * Handle a replacement for the given request.
- * @param blk A pointer to the block, usually NULL
- * @param pkt The memory request to satisfy.
- * @param new_state The new state of the block.
- * @param writebacks A list to store any generated writebacks.
- */
- BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
- CacheBlk::State new_state, PacketList &writebacks);
-
/**
- * Does all the processing necessary to perform the provided request.
- * @param pkt The memory request to perform.
- * @param lat The latency of the access.
- * @param writebacks List for any writebacks that need to be performed.
- * @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * Store the outstanding requests that we are expecting snoop
+ * responses from so we can determine which snoop responses we
+ * generated and which ones were merely forwarded.
*/
- bool access(PacketPtr pkt, BlkType *&blk, int &lat);
+ std::unordered_set<RequestPtr> outstandingSnoop;
+ protected:
/**
- *Handle doing the Compare and Swap function for SPARC.
+ * Turn line-sized writes into WriteInvalidate transactions.
*/
- void cmpAndSwap(BlkType *blk, PacketPtr pkt);
+ void promoteWholeLineWrites(PacketPtr pkt);
- /**
- * Populates a cache block and handles all outstanding requests for the
- * satisfied fill request. This version takes two memory requests. One
- * contains the fill data, the other is an optional target to satisfy.
- * Used for Cache::probe.
- * @param pkt The memory request with the fill data.
- * @param blk The cache block if it already exists.
- * @param writebacks List for any writebacks that need to be performed.
- * @return Pointer to the new cache block.
- */
- BlkType *handleFill(PacketPtr pkt, BlkType *blk,
- PacketList &writebacks);
+ bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
+ PacketList &writebacks) override;
- void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
- bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
+ void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
+ Tick request_time) override;
- void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
- bool already_copied);
+ void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
+ Tick forward_time,
+ Tick request_time) override;
- /**
- * Sets the blk to the new state.
- * @param blk The cache block being snooped.
- * @param new_state The new coherence state for the block.
- */
- void handleSnoop(PacketPtr ptk, BlkType *blk,
- bool is_timing, bool is_deferred);
+ void recvTimingReq(PacketPtr pkt) override;
- /**
- * Create a writeback request for the given block.
- * @param blk The block to writeback.
- * @return The writeback request for the block.
- */
- PacketPtr writebackBlk(BlkType *blk);
+ void doWritebacks(PacketList& writebacks, Tick forward_time) override;
- public:
+ void doWritebacksAtomic(PacketList& writebacks) override;
- class Params
- {
- public:
- TagStore *tags;
- BaseCache::Params baseParams;
- BasePrefetcher*prefetcher;
- bool prefetchAccess;
- const bool doFastWrites;
- const bool prefetchMiss;
+ void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
+ PacketList& writebacks) override;
- Params(TagStore *_tags,
- BaseCache::Params params,
- BasePrefetcher *_prefetcher,
- bool prefetch_access, int hit_latency,
- bool do_fast_writes,
- bool prefetch_miss)
- : tags(_tags),
- baseParams(params),
- prefetcher(_prefetcher), prefetchAccess(prefetch_access),
- doFastWrites(do_fast_writes),
- prefetchMiss(prefetch_miss)
- {
- }
- };
+ void recvTimingSnoopReq(PacketPtr pkt) override;
- /** Instantiates a basic cache object. */
- Cache(const std::string &_name, Params ¶ms);
+ void recvTimingSnoopResp(PacketPtr pkt) override;
- virtual Port *getPort(const std::string &if_name, int idx = -1);
- virtual void deletePortRefs(Port *p);
+ Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
+ PacketList &writebacks) override;
- void regStats();
+ Tick recvAtomic(PacketPtr pkt) override;
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
- */
- bool timingAccess(PacketPtr pkt);
-
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
- */
- Tick atomicAccess(PacketPtr pkt);
+ Tick recvAtomicSnoop(PacketPtr pkt) override;
- /**
- * Performs the access specified by the request.
- * @param pkt The request to perform.
- * @return The result of the access.
- */
- void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
+ void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
+ bool deferred_response = false,
+ bool pending_downgrade = false) override;
- /**
- * Handles a response (cache line fill/write ack) from the bus.
- * @param pkt The request being responded to.
- */
- void handleResponse(PacketPtr pkt);
+ void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
+ bool already_copied, bool pending_inval);
/**
- * Snoops bus transactions to maintain coherence.
- * @param pkt The current bus transaction.
+ * Perform an upward snoop if needed, and update the block state
+ * (possibly invalidating the block). Also create a response if required.
+ *
+ * @param pkt Snoop packet
+ * @param blk Cache block being snooped
+ * @param is_timing Timing or atomic for the response
+ * @param is_deferred Is this a deferred snoop or not?
+ * @param pending_inval Do we have a pending invalidation?
+ *
+ * @return The snoop delay incurred by the upwards snoop
*/
- void snoopTiming(PacketPtr pkt);
+ uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
+ bool is_timing, bool is_deferred, bool pending_inval);
- /**
- * Snoop for the provided request in the cache and return the estimated
- * time of completion.
- * @param pkt The memory request to snoop
- * @return The estimated completion time.
- */
- Tick snoopAtomic(PacketPtr pkt);
+ M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
/**
- * Squash all requests associated with specified thread.
- * intended for use by I-cache.
- * @param threadNum The thread to squash.
+ * Create a CleanEvict request for the given block.
+ *
+ * @param blk The block to evict.
+ * @return The CleanEvict request for the block.
*/
- void squash(int threadNum);
+ PacketPtr cleanEvictBlk(CacheBlk *blk);
- /**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
- */
- PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
- bool needsExclusive);
- MSHR *getNextMSHR();
- PacketPtr getTimingPacket();
+ PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
+ bool needs_writable,
+ bool is_whole_line_write) const override;
/**
- * Marks a request as in service (sent on the bus). This can have side
- * effect since storage for no response commands is deallocated once they
- * are successfully sent.
- * @param pkt The request that was sent on the bus.
+ * Send up a snoop request and find cached copies. If cached copies are
+ * found, set the BLOCK_CACHED flag in pkt.
*/
- void markInService(MSHR *mshr);
+ bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
- /**
- * Perform the given writeback request.
- * @param pkt The writeback request.
- */
- void doWriteback(PacketPtr pkt);
+ public:
+ /** Instantiates a basic cache object. */
+ Cache(const CacheParams *p);
/**
- * Return whether there are any outstanding misses.
+ * Take an MSHR, turn it into a suitable downstream packet, and
+ * send it out. This construct allows a queue entry to choose a suitable
+ * approach based on its type.
+ *
+ * @param mshr The MSHR to turn into a packet and send
+ * @return True if the port is waiting for a retry
*/
- bool outstandingMisses() const
- {
- return mshrQueue.allocated != 0;
- }
-
- CacheBlk *findBlock(Addr addr) {
- return tags->findBlock(addr);
- }
-
- bool inCache(Addr addr) {
- return (tags->findBlock(addr) != 0);
- }
-
- bool inMissQueue(Addr addr) {
- return (mshrQueue.findMatch(addr) != 0);
- }
+ bool sendMSHRQueuePacket(MSHR* mshr) override;
};
-#endif // __CACHE_HH__
+#endif // __MEM_CACHE_CACHE_HH__