/*
+ * Copyright (c) 2012-2018 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2020 Inria
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Erik Hallnor
*/
/** @file
* Definitions of a simple cache block class.
*/
-#ifndef __CACHE_BLK_HH__
-#define __CACHE_BLK_HH__
+#ifndef __MEM_CACHE_CACHE_BLK_HH__
+#define __MEM_CACHE_CACHE_BLK_HH__
+#include <cassert>
+#include <cstdint>
+#include <iosfwd>
#include <list>
+#include <string>
-#include "sim/root.hh" // for Tick
-#include "arch/isa_traits.hh" // for Addr
+#include "base/printable.hh"
+#include "base/types.hh"
+#include "mem/cache/tags/tagged_entry.hh"
+#include "mem/packet.hh"
#include "mem/request.hh"
-
-/**
- * Cache block status bit assignments
- */
-enum CacheBlkStatusBits {
- /** valid, readable */
- BlkValid = 0x01,
- /** write permission */
- BlkWritable = 0x02,
- /** dirty (modified) */
- BlkDirty = 0x04,
- /** compressed */
- BlkCompressed = 0x08,
- /** block was referenced */
- BlkReferenced = 0x10,
- /** block was a hardware prefetch yet unaccessed*/
- BlkHWPrefetched = 0x20
-};
+#include "sim/core.hh"
/**
* A Basic Cache block.
- * Contains the tag, status, and a pointer to data.
+ * Contains information regarding its coherence, prefetching status, as
+ * well as a pointer to its data.
*/
-class CacheBlk
+class CacheBlk : public TaggedEntry
{
public:
- /** The address space ID of this block. */
- int asid;
- /** Data block tag value. */
- Addr tag;
+ /**
+ * Cache block's enum listing the supported coherence bits. The valid
+ * bit is not defined here because it is part of a TaggedEntry.
+ */
+ enum CoherenceBits : unsigned
+ {
+ /** write permission */
+ WritableBit = 0x02,
+ /**
+ * Read permission. Note that a block can be valid but not readable
+ * if there is an outstanding write upgrade miss.
+ */
+ ReadableBit = 0x04,
+ /** dirty (modified) */
+ DirtyBit = 0x08,
+
+ /**
+ * Helper enum value that includes all other bits. Whenever a new
+ * bits is added, this should be updated.
+ */
+ AllBits = 0x0E,
+ };
+
/**
* Contains a copy of the data in this block for easy access. This is used
* for efficient execution when the data could be actually stored in
* referenced by this block.
*/
uint8_t *data;
- /** the number of bytes stored in this block. */
- int size;
-
- /** block state: OR of CacheBlkStatusBit */
- typedef unsigned State;
-
- /** The current status of this block. @sa CacheBlockStatusBits */
- State status;
-
- /** Which curTick will this block be accessable */
- Tick whenReady;
/**
- * The set this block belongs to.
- * @todo Move this into subclasses when we fix CacheTags to use them.
+ * Which curTick() will this block be accessible. Its value is only
+ * meaningful if the block is valid.
*/
- int set;
-
- /** Number of references to this block since it was brought in. */
- int refCount;
+ Tick whenReady;
protected:
/**
*/
class Lock {
public:
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ ContextID contextId; // locking context
+ Addr lowAddr; // low address of lock range
+ Addr highAddr; // high address of lock range
- // check for matching execution context
- bool matchesContext(Request *req)
+ // check for matching execution context, and an address that
+ // is within the lock
+ bool matches(const RequestPtr &req) const
{
- return (cpuNum == req->getCpuNum() &&
- threadNum == req->getThreadNum());
+ Addr req_low = req->getPaddr();
+ Addr req_high = req_low + req->getSize() -1;
+ return (contextId == req->contextId()) &&
+ (req_low >= lowAddr) && (req_high <= highAddr);
}
- Lock(Request *req)
- : cpuNum(req->getCpuNum()), threadNum(req->getThreadNum())
+ // check if a request is intersecting and thus invalidating the lock
+ bool intersects(const RequestPtr &req) const
+ {
+ Addr req_low = req->getPaddr();
+ Addr req_high = req_low + req->getSize() - 1;
+
+ return (req_low <= highAddr) && (req_high >= lowAddr);
+ }
+
+ Lock(const RequestPtr &req)
+ : contextId(req->contextId()),
+ lowAddr(req->getPaddr()),
+ highAddr(lowAddr + req->getSize() - 1)
{
}
};
std::list<Lock> lockList;
public:
+ CacheBlk() : TaggedEntry(), data(nullptr), _tickInserted(0)
+ {
+ invalidate();
+ }
- CacheBlk()
- : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
- set(-1), refCount(0)
- {}
+ CacheBlk(const CacheBlk&) = delete;
+ CacheBlk& operator=(const CacheBlk&) = delete;
+ virtual ~CacheBlk() {};
/**
- * Copy the state of the given block into this one.
- * @param rhs The block to copy.
- * @return a const reference to this block.
+ * Invalidate the block and clear all state.
*/
- const CacheBlk& operator=(const CacheBlk& rhs)
+ virtual void invalidate()
{
- asid = rhs.asid;
- tag = rhs.tag;
- data = rhs.data;
- size = rhs.size;
- status = rhs.status;
- whenReady = rhs.whenReady;
- set = rhs.set;
- refCount = rhs.refCount;
- return *this;
+ TaggedEntry::invalidate();
+
+ clearPrefetched();
+ clearCoherenceBits(AllBits);
+
+ setTaskId(ContextSwitchTaskId::Unknown);
+ whenReady = MaxTick;
+ setRefCount(0);
+ setSrcRequestorId(Request::invldRequestorId);
+ lockList.clear();
}
/**
- * Checks the write permissions of this block.
- * @return True if the block is writable.
+ * Sets the corresponding coherence bits.
+ *
+ * @param bits The coherence bits to be set.
*/
- bool isWritable() const
+ void
+ setCoherenceBits(unsigned bits)
{
- const int needed_bits = BlkWritable | BlkValid;
- return (status & needed_bits) == needed_bits;
+ assert(isValid());
+ coherence |= bits;
}
/**
- * Checks that a block is valid (readable).
- * @return True if the block is valid.
+ * Clear the corresponding coherence bits.
+ *
+ * @param bits The coherence bits to be cleared.
+ */
+ void clearCoherenceBits(unsigned bits) { coherence &= ~bits; }
+
+ /**
+ * Checks the given coherence bits are set.
+ *
+ * @return True if the block is readable.
*/
- bool isValid() const
+ bool
+ isSet(unsigned bits) const
{
- return (status & BlkValid) != 0;
+ return isValid() && (coherence & bits);
}
/**
- * Check to see if a block has been written.
- * @return True if the block is dirty.
+ * Check if this block was the result of a hardware prefetch, yet to
+ * be touched.
+ * @return True if the block was a hardware prefetch, unaccesed.
+ */
+ bool wasPrefetched() const { return _prefetched; }
+
+ /**
+ * Clear the prefetching bit. Either because it was recently used, or due
+ * to the block being invalidated.
+ */
+ void clearPrefetched() { _prefetched = false; }
+
+ /** Marks this blocks as a recently prefetched block. */
+ void setPrefetched() { _prefetched = false; }
+
+ /**
+ * Get tick at which block's data will be available for access.
+ *
+ * @return Data ready tick.
*/
- bool isModified() const
+ Tick getWhenReady() const
{
- return (status & BlkDirty) != 0;
+ assert(whenReady != MaxTick);
+ return whenReady;
}
/**
- * Check to see if this block contains compressed data.
- * @return True iF the block's data is compressed.
+ * Set tick at which block's data will be available for access. The new
+ * tick must be chronologically sequential with respect to previous
+ * accesses.
+ *
+ * @param tick New data ready tick.
*/
- bool isCompressed() const
+ void setWhenReady(const Tick tick)
{
- return (status & BlkCompressed) != 0;
+ assert(tick >= _tickInserted);
+ whenReady = tick;
}
+ /** Get the task id associated to this block. */
+ uint32_t getTaskId() const { return _taskId; }
+
+ /** Get the requestor id associated to this block. */
+ uint32_t getSrcRequestorId() const { return _srcRequestorId; }
+
+ /** Get the number of references to this block since insertion. */
+ unsigned getRefCount() const { return _refCount; }
+
+ /** Get the number of references to this block since insertion. */
+ void increaseRefCount() { _refCount++; }
+
/**
- * Check if this block has been referenced.
- * @return True if the block has been referenced.
+ * Get the block's age, that is, the number of ticks since its insertion.
+ *
+ * @return The block's age.
*/
- bool isReferenced() const
+ Tick
+ getAge() const
{
- return (status & BlkReferenced) != 0;
+ assert(_tickInserted <= curTick());
+ return curTick() - _tickInserted;
}
/**
- * Check if this block was the result of a hardware prefetch, yet to
- * be touched.
- * @return True if the block was a hardware prefetch, unaccesed.
+ * Set member variables when a block insertion occurs. Resets reference
+ * count to 1 (the insertion counts as a reference), and touch block if
+ * it hadn't been touched previously. Sets the insertion tick to the
+ * current tick. Marks the block valid.
+ *
+ * @param tag Block address tag.
+ * @param is_secure Whether the block is in secure space or not.
+ * @param src_requestor_ID The source requestor ID.
+ * @param task_ID The new task ID.
*/
- bool isPrefetch() const
+ void insert(const Addr tag, const bool is_secure,
+ const int src_requestor_ID, const uint32_t task_ID);
+ using TaggedEntry::insert;
+
+ /**
+ * Track the fact that a local locked was issued to the
+ * block. Invalidate any previous LL to the same address.
+ */
+ void trackLoadLocked(PacketPtr pkt)
{
- return (status & BlkHWPrefetched) != 0;
+ assert(pkt->isLLSC());
+ auto l = lockList.begin();
+ while (l != lockList.end()) {
+ if (l->intersects(pkt->req))
+ l = lockList.erase(l);
+ else
+ ++l;
+ }
+
+ lockList.emplace_front(pkt->req);
}
/**
- * Track the fact that a local locked was issued to the block. If
- * multiple LLs get issued from the same context we could have
- * redundant records on the list, but that's OK, as they'll all
- * get blown away at the next store.
+ * Clear the any load lock that intersect the request, and is from
+ * a different context.
*/
- void trackLoadLocked(Request *req)
+ void clearLoadLocks(const RequestPtr &req)
{
- assert(req->isLocked());
- lockList.push_front(Lock(req));
+ auto l = lockList.begin();
+ while (l != lockList.end()) {
+ if (l->intersects(req) && l->contextId != req->contextId()) {
+ l = lockList.erase(l);
+ } else {
+ ++l;
+ }
+ }
}
/**
- * Clear the list of valid load locks. Should be called whenever
- * block is written to or invalidated.
+ * Pretty-print tag, set and way, and interpret state bits to readable form
+ * including mapping to a MOESI state.
+ *
+ * @return string with basic state information
*/
- void clearLoadLocks() { lockList.clear(); }
+ std::string
+ print() const override
+ {
+ /**
+ * state M O E S I
+ * writable 1 0 1 0 0
+ * dirty 1 1 0 0 0
+ * valid 1 1 1 1 0
+ *
+ * state writable dirty valid
+ * M 1 1 1
+ * O 0 1 1
+ * E 1 0 1
+ * S 0 0 1
+ * I 0 0 0
+ *
+ * Note that only one cache ever has a block in Modified or
+ * Owned state, i.e., only one cache owns the block, or
+ * equivalently has the DirtyBit bit set. However, multiple
+ * caches on the same path to memory can have a block in the
+ * Exclusive state (despite the name). Exclusive means this
+ * cache has the only copy at this level of the hierarchy,
+ * i.e., there may be copies in caches above this cache (in
+ * various states), but there are no peers that have copies on
+ * this branch of the hierarchy, and no caches at or above
+ * this level on any other branch have copies either.
+ **/
+ unsigned state =
+ isSet(WritableBit) << 2 | isSet(DirtyBit) << 1 | isValid();
+ char s = '?';
+ switch (state) {
+ case 0b111: s = 'M'; break;
+ case 0b011: s = 'O'; break;
+ case 0b101: s = 'E'; break;
+ case 0b001: s = 'S'; break;
+ case 0b000: s = 'I'; break;
+ default: s = 'T'; break; // @TODO add other types
+ }
+ return csprintf("state: %x (%c) writable: %d readable: %d "
+ "dirty: %d | %s", coherence, s, isSet(WritableBit),
+ isSet(ReadableBit), isSet(DirtyBit), TaggedEntry::print());
+ }
/**
* Handle interaction of load-locked operations and stores.
* @return True if write should proceed, false otherwise. Returns
* false only in the case of a failed store conditional.
*/
- bool checkWrite(Request *req)
+ bool checkWrite(PacketPtr pkt)
{
- if (req->isLocked()) {
+ assert(pkt->isWrite());
+
+ // common case
+ if (!pkt->isLLSC() && lockList.empty())
+ return true;
+
+ const RequestPtr &req = pkt->req;
+
+ if (pkt->isLLSC()) {
// it's a store conditional... have to check for matching
// load locked.
bool success = false;
- for (std::list<Lock>::iterator i = lockList.begin();
- i != lockList.end(); ++i)
- {
- if (i->matchesContext(req)) {
- // it's a store conditional, and as far as the memory
- // system can tell, the requesting context's lock is
- // still valid.
+ auto l = lockList.begin();
+ while (!success && l != lockList.end()) {
+ if (l->matches(pkt->req)) {
+ // it's a store conditional, and as far as the
+ // memory system can tell, the requesting
+ // context's lock is still valid.
success = true;
- break;
+ lockList.erase(l);
+ } else {
+ ++l;
}
}
- req->setScResult(success ? 1 : 0);
- clearLoadLocks();
+ req->setExtraData(success ? 1 : 0);
+ // clear any intersected locks from other contexts (our LL
+ // should already have cleared them)
+ clearLoadLocks(req);
return success;
} else {
- // for *all* stores (conditional or otherwise) we have to
- // clear the list of load-locks as they're all invalid now.
- clearLoadLocks();
+ // a normal write, if there is any lock not from this
+ // context we clear the list, thus for a private cache we
+ // never clear locks on normal writes
+ clearLoadLocks(req);
return true;
}
}
+
+ protected:
+ /** The current coherence status of this block. @sa CoherenceBits */
+ unsigned coherence;
+
+ // The following setters have been marked as protected because their
+ // respective variables should only be modified at 2 moments:
+ // invalidation and insertion. Because of that, they shall only be
+ // called by the functions that perform those actions.
+
+ /** Set the task id value. */
+ void setTaskId(const uint32_t task_id) { _taskId = task_id; }
+
+ /** Set the source requestor id. */
+ void setSrcRequestorId(const uint32_t id) { _srcRequestorId = id; }
+
+ /** Set the number of references to this block since insertion. */
+ void setRefCount(const unsigned count) { _refCount = count; }
+
+ /** Set the current tick as this block's insertion tick. */
+ void setTickInserted() { _tickInserted = curTick(); }
+
+ private:
+ /** Task Id associated with this block */
+ uint32_t _taskId;
+
+ /** holds the source requestor ID for this block. */
+ int _srcRequestorId;
+
+ /** Number of references to this block since it was brought in. */
+ unsigned _refCount;
+
+ /**
+ * Tick on which the block was inserted in the cache. Its value is only
+ * meaningful if the block is valid.
+ */
+ Tick _tickInserted;
+
+ /** Whether this block is an unaccessed hardware prefetch. */
+ bool _prefetched;
+};
+
+/**
+ * Special instance of CacheBlk for use with tempBlk that deals with its
+ * block address regeneration.
+ * @sa Cache
+ */
+class TempCacheBlk final : public CacheBlk
+{
+ private:
+ /**
+ * Copy of the block's address, used to regenerate tempBlock's address.
+ */
+ Addr _addr;
+
+ public:
+ /**
+ * Creates a temporary cache block, with its own storage.
+ * @param size The size (in bytes) of this cache block.
+ */
+ TempCacheBlk(unsigned size) : CacheBlk()
+ {
+ data = new uint8_t[size];
+ }
+ TempCacheBlk(const TempCacheBlk&) = delete;
+ TempCacheBlk& operator=(const TempCacheBlk&) = delete;
+ ~TempCacheBlk() { delete [] data; };
+
+ /**
+ * Invalidate the block and clear all state.
+ */
+ void invalidate() override {
+ CacheBlk::invalidate();
+
+ _addr = MaxAddr;
+ }
+
+ void
+ insert(const Addr addr, const bool is_secure) override
+ {
+ CacheBlk::insert(addr, is_secure);
+ _addr = addr;
+ }
+
+ /**
+ * Get block's address.
+ *
+ * @return addr Address value.
+ */
+ Addr getAddr() const
+ {
+ return _addr;
+ }
+};
+
+/**
+ * Simple class to provide virtual print() method on cache blocks
+ * without allocating a vtable pointer for every single cache block.
+ * Just wrap the CacheBlk object in an instance of this before passing
+ * to a function that requires a Printable object.
+ */
+class CacheBlkPrintWrapper : public Printable
+{
+ CacheBlk *blk;
+ public:
+ CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
+ virtual ~CacheBlkPrintWrapper() {}
+ void print(std::ostream &o, int verbosity = 0,
+ const std::string &prefix = "") const;
};
-#endif //__CACHE_BLK_HH__
+#endif //__MEM_CACHE_CACHE_BLK_HH__
projects / gem5.git / blobdiff