Fix problems with unCacheable addresses in timing-coherence

[gem5.git] / src / mem / cache / cache_builder.cc

diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 8758dc57a4ae08d9d1e0b6f8484909e3e4fc0ce5..05a149a1cdce1191cf39a3869f8336794b2bb4e2 100644 (file)
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -230,7 +230,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
         Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
                                                        do_copy, base_params, \
                                                        /*in_bus, out_bus,*/ pf,  \
-                                                       prefetch_access); \
+                                                       prefetch_access, hit_latency); \
         Cache<CacheTags<t, comp>, b, c> *retval =                      \
             new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
                                                 params);               \
@@ -242,7 +242,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
         retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
         out_bus->rangeChange();                                                \
         return retval;                                                 \
-*/return true;                                                          \
+*/return retval;                                                          \
     } while (0)
 
 #define BUILD_CACHE_PANIC(x) do {                      \