if (pkt->isResponse())
handleResponse(pkt);
else
- snoopProbe(pkt);
+ return snoopProbe(pkt);
}
//Fix this timing info
return hitLatency;
prefetchAccess(params.prefetchAccess),
tags(params.tags), missQueue(params.missQueue),
coherence(params.coherence), prefetcher(params.prefetcher),
- doCopy(params.doCopy), blockOnCopy(params.blockOnCopy)
+ doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
+ hitLatency(params.hitLatency)
{
-//FIX BUS POINTERS
-// if (params.in == NULL) {
- topLevelCache = true;
-// }
-//PLEASE FIX THIS, BUS SIZES NOT BEING USED
- tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
+ tags->setCache(this);
tags->setPrefetcher(prefetcher);
missQueue->setCache(this);
missQueue->setPrefetcher(prefetcher);
void
Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, bool success)
{
- if (success && !(pkt->flags & NACKED_LINE)) {
- missQueue->markInService(pkt, mshr);
+ if (success && !(pkt && (pkt->flags & NACKED_LINE))) {
+ if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)
+ && (pkt && (pkt->flags & SATISFIED))) {
+ //Writeback, clean up the non copy version of the packet
+ delete pkt;
+ }
+ missQueue->markInService(mshr->pkt, mshr);
//Temp Hack for UPGRADES
- if (pkt->cmd == Packet::UpgradeReq) {
+ if (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq) {
+ assert(pkt); //Upgrades need to be fixed
pkt->flags &= ~CACHE_LINE_FILL;
BlkType *blk = tags->findBlock(pkt);
CacheBlk::State old_state = (blk) ? blk->status : 0;
CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
- DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
- pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
+ if (old_state != new_state)
+ DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
+ pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
//Set the state on the upgrade
memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
PacketList writebacks;
pkt->flags &= ~NACKED_LINE;
pkt->flags &= ~SATISFIED;
pkt->flags &= ~SNOOP_COMMIT;
+
+//Rmove copy from mshr
+ delete mshr->pkt;
+ mshr->pkt = pkt;
+
missQueue->restoreOrigCmd(pkt);
}
}
{
BlkType *blk = NULL;
if (pkt->senderState) {
+ //Delete temp copy in MSHR, restore it.
+ delete ((MSHR*)pkt->senderState)->pkt;
+ ((MSHR*)pkt->senderState)->pkt = pkt;
if (pkt->result == Packet::Nacked) {
//pkt->reinitFromRequest();
warn("NACKs from devices not connected to the same bus not implemented\n");
CacheBlk::State old_state = (blk) ? blk->status : 0;
PacketList writebacks;
CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
- DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
- pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
+ if (old_state != new_state)
+ DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
+ pkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
new_state, writebacks, pkt);
while (!writebacks.empty()) {
return coherence->getPacket();
}
+template<class TagStore, class Buffering, class Coherence>
+void
+Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt,
+ MSHR *cshr,
+ bool success)
+{
+ coherence->sendResult(pkt, cshr, success);
+}
+
template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
{
+ if (pkt->req->isUncacheable()) {
+ //Can't get a hit on an uncacheable address
+ //Revisit this for multi level coherence
+ return;
+ }
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
- if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
+ if (coherence->hasProtocol()) { //@todo Move this into handle bus req
//If we find an mshr, and it is in service, we need to NACK or invalidate
if (mshr) {
if (mshr->inService) {
int lat;
BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
+ DPRINTF(Cache, "%s %x %s blk_addr: %x\n", pkt->cmdString(),
+ pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
+ pkt->getAddr() & ~((Addr)blkSize - 1));
+
if (!blk) {
// Need to check for outstanding misses and writes
Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
busPkt->time = curTick;
+ DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n",
+ busPkt->cmdString(),
+ busPkt->getAddr() & (((ULL(1))<<48)-1),
+ busPkt->getAddr() & ~((Addr)blkSize - 1));
+
lat = memSidePort->sendAtomic(busPkt);
//Be sure to flip the response to a request for coherence
*/ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
CacheBlk::State old_state = (blk) ? blk->status : 0;
+ CacheBlk::State new_state = coherence->getNewState(busPkt, old_state);
+ DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n",
+ busPkt->cmdString(),
+ busPkt->getAddr() & (((ULL(1))<<48)-1), old_state);
+ if (old_state != new_state)
+ DPRINTF(Cache, "Block for blk addr %x moving from state %i to %i\n",
+ busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state);
+
tags->handleFill(blk, busPkt,
- coherence->getNewState(busPkt, old_state),
+ new_state,
writebacks, pkt);
+ //Free the packet
+ delete busPkt;
+
// Handle writebacks if needed
while (!writebacks.empty()){
- memSidePort->sendAtomic(writebacks.front());
+ Packet *wbPkt = writebacks.front();
+ memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
+ delete wbPkt;
}
return lat + hitLatency;
} else {
// Still need to change data in all locations.
otherSidePort->sendFunctional(pkt);
}
- return curTick + lat;
+ return hitLatency;
}
fatal("Probe not handled.\n");
return 0;
projects / gem5.git / blobdiff