Merge zizzer:/z/m5/Bitkeeper/newmem

[gem5.git] / src / mem / cache / cache_impl.hh

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index db012920f3f870d08b02f13bcbeb9df61016ec1e..b215960c43ddf33f216da097fe3158946068ab3b 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -53,8 +53,6 @@
 
 #include "sim/sim_events.hh" // for SimExitEvent
 
-using namespace std;
-
 template<class TagStore, class Buffering, class Coherence>
 bool
 Cache<TagStore,Buffering,Coherence>::
@@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
 
         // There can be many matching outstanding writes.
-        vector<MSHR*> writes;
+        std::vector<MSHR*> writes;
         missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
 
         if (!update) {