inorder: ctxt switch stats

[gem5.git] / src / mem / cache / mshr.cc

diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 6537f63439f5bc1cbd86577534e44591463f5fea..100e6126ad616389192fa25b52b37ac83c6ff51a 100644 (file)
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -34,16 +34,16 @@
  * Miss Status and Handling Register (MSHR) definitions.
  */
 
-#include <assert.h>
+#include <algorithm>
+#include <cassert>
 #include <string>
 #include <vector>
-#include <algorithm>
 
-#include "mem/cache/mshr.hh"
-#include "sim/core.hh" // for curTick
-#include "sim/host.hh"
 #include "base/misc.hh"
+#include "base/types.hh"
 #include "mem/cache/cache.hh"
+#include "mem/cache/mshr.hh"
+#include "sim/core.hh"
 
 using namespace std;
 
@@ -51,7 +51,7 @@ MSHR::MSHR()
 {
     inService = false;
     ntargets = 0;
-    threadNum = -1;
+    threadNum = InvalidThreadID;
     targets = new TargetList();
     deferredTargets = new TargetList();
 }
@@ -64,9 +64,9 @@ MSHR::TargetList::TargetList()
 
 inline void
 MSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
-                      Counter order, bool cpuSide, bool markPending)
+                      Counter order, Target::Source source, bool markPending)
 {
-    if (cpuSide) {
+    if (source != Target::FromSnoop) {
         if (pkt->needsExclusive()) {
             needsExclusive = true;
         }
@@ -84,7 +84,7 @@ MSHR::TargetList::add(PacketPtr pkt, Tick readyTime,
         }
     }
 
-    push_back(Target(pkt, readyTime, order, cpuSide, markPending));
+    push_back(Target(pkt, readyTime, order, source, markPending));
 }
 
 
@@ -141,7 +141,14 @@ print(std::ostream &os, int verbosity, const std::string &prefix) const
 {
     ConstIterator end_i = end();
     for (ConstIterator i = begin(); i != end_i; ++i) {
-        ccprintf(os, "%s%s: ", prefix, i->isCpuSide() ? "cpu" : "mem");
+        const char *s;
+        switch (i->source) {
+          case Target::FromCPU: s = "FromCPU";
+          case Target::FromSnoop: s = "FromSnoop";
+          case Target::FromPrefetcher: s = "FromPrefetcher";
+          default: s = "";
+        }
+        ccprintf(os, "%s%s: ", prefix, s);
         i->pkt->print(os, verbosity, "");
     }
 }
@@ -156,16 +163,18 @@ MSHR::allocate(Addr _addr, int _size, PacketPtr target,
     readyTime = whenReady;
     order = _order;
     assert(target);
-    isCacheFill = false;
+    isForward = false;
     _isUncacheable = target->req->isUncacheable();
     inService = false;
     downstreamPending = false;
     threadNum = 0;
     ntargets = 1;
-    // Don't know of a case where we would allocate a new MSHR for a
-    // snoop (mem-side request), so set cpuSide to true here.
     assert(targets->isReset());
-    targets->add(target, whenReady, _order, true, true);
+    // Don't know of a case where we would allocate a new MSHR for a
+    // snoop (mem-side request), so set source according to request here
+    Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
+        Target::FromPrefetcher : Target::FromCPU;
+    targets->add(target, whenReady, _order, source, true);
     assert(deferredTargets->isReset());
     pendingInvalidate = false;
     pendingShared = false;
@@ -187,7 +196,7 @@ bool
 MSHR::markInService()
 {
     assert(!inService);
-    if (isSimpleForward()) {
+    if (isForwardNoResponse()) {
         // we just forwarded the request packet & don't expect a
         // response, so get rid of it
         assert(getNumTargets() == 1);
@@ -230,17 +239,22 @@ MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
     //   comes back (but before this target is processed)
     // - the outstanding request is for a non-exclusive block and this
     //   target requires an exclusive block
+
+    // assume we'd never issue a prefetch when we've got an
+    // outstanding miss
+    assert(pkt->cmd != MemCmd::HardPFReq);
+
     if (inService &&
         (!deferredTargets->empty() || pendingInvalidate ||
          (!targets->needsExclusive && pkt->needsExclusive()))) {
         // need to put on deferred list
-        deferredTargets->add(pkt, whenReady, _order, true, true);
+        deferredTargets->add(pkt, whenReady, _order, Target::FromCPU, true);
     } else {
         // No request outstanding, or still OK to append to
         // outstanding request: append to regular target list.  Only
         // mark pending if current request hasn't been issued yet
         // (isn't in service).
-        targets->add(pkt, whenReady, _order, true, !inService);
+        targets->add(pkt, whenReady, _order, Target::FromCPU, !inService);
     }
 
     ++ntargets;
@@ -291,7 +305,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
         // actual target device (typ. PhysicalMemory) will delete the
         // packet on reception, so we need to save a copy here
         PacketPtr cp_pkt = new Packet(pkt, true);
-        targets->add(cp_pkt, curTick, _order, false,
+        targets->add(cp_pkt, curTick, _order, Target::FromSnoop,
                      downstreamPending && targets->needsExclusive);
         ++ntargets;
 
@@ -403,7 +417,8 @@ MSHR::print(std::ostream &os, int verbosity, const std::string &prefix) const
 {
     ccprintf(os, "%s[%x:%x] %s %s %s state: %s %s %s %s\n",
              prefix, addr, addr+size-1,
-             isCacheFill ? "Fill" : "",
+             isForward ? "Forward" : "",
+             isForwardNoResponse() ? "ForwNoResp" : "",
              needsExclusive() ? "Excl" : "",
              _isUncacheable ? "Unc" : "",
              inService ? "InSvc" : "",