mem-cache: Fix set and way of sub-entries

[gem5.git] / src / mem / cache / noncoherent_cache.cc

diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 5edd435c6eded8c2c20784f67404705aef3c77c6..9a2a1db9d85a3c412e3d380b31e06eefc0c68dbb 100644 (file)
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -243,11 +243,10 @@ NoncoherentCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
 
 void
 NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
-                                     CacheBlk *blk, PacketList &writebacks)
+                                     CacheBlk *blk)
 {
-    MSHR::Target *initial_tgt = mshr->getTarget();
     // First offset for critical word first calculations
-    const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
+    const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
 
     MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
     for (auto &target: targets) {
@@ -288,7 +287,7 @@ NoncoherentCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
 
             // Reset the bus additional time as it is now accounted for
             tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
-            cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true);
+            cpuSidePort.schedTimingResp(tgt_pkt, completion_time);
             break;
 
           case MSHR::Target::FromPrefetcher: