mem-cache: Make StridePrefetcher use Replacement Policies

[gem5.git] / src / mem / cache / prefetch / Prefetcher.py

diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 320755d7531e5d09d84ff47383f9ae92995ec34c..bae235d84b492bfd9fa411c5afe24ba2d3f1272e 100644 (file)
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -40,20 +40,60 @@
 #          Mitch Hayenga
 
 from ClockedObject import ClockedObject
+from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
+from ReplacementPolicies import *
+
+class HWPProbeEvent(object):
+    def __init__(self, prefetcher, obj, *listOfNames):
+        self.obj = obj
+        self.prefetcher = prefetcher
+        self.names = listOfNames
+
+    def register(self):
+        if self.obj:
+            for name in self.names:
+                self.prefetcher.getCCObject().addEventProbe(
+                    self.obj.getCCObject(), name)
 
 class BasePrefetcher(ClockedObject):
     type = 'BasePrefetcher'
     abstract = True
     cxx_header = "mem/cache/prefetch/base.hh"
+    cxx_exports = [
+        PyBindMethod("addEventProbe"),
+    ]
     sys = Param.System(Parent.any, "System this prefetcher belongs to")
 
+    # Get the block size from the parent (system)
+    block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
+
     on_miss = Param.Bool(False, "Only notify prefetcher on misses")
     on_read = Param.Bool(True, "Notify prefetcher on reads")
     on_write = Param.Bool(True, "Notify prefetcher on writes")
     on_data  = Param.Bool(True, "Notify prefetcher on data accesses")
     on_inst  = Param.Bool(True, "Notify prefetcher on instruction accesses")
+    prefetch_on_access = Param.Bool(Parent.prefetch_on_access,
+        "Notify the hardware prefetcher on every access (not just misses)")
+
+    _events = []
+    def addEvent(self, newObject):
+        self._events.append(newObject)
+
+    # Override the normal SimObject::regProbeListeners method and
+    # register deferred event handlers.
+    def regProbeListeners(self):
+        for event in self._events:
+           event.register()
+        self.getCCObject().regProbeListeners()
+
+    def listenFromProbe(self, simObj, *probeNames):
+        if not isinstance(simObj, SimObject):
+            raise TypeError("argument must be of SimObject type")
+        if len(probeNames) <= 0:
+            raise TypeError("probeNames must have at least one element")
+        self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
 
 class QueuedPrefetcher(BasePrefetcher):
     type = "QueuedPrefetcher"
@@ -73,6 +113,9 @@ class StridePrefetcher(QueuedPrefetcher):
     cxx_class = 'StridePrefetcher'
     cxx_header = "mem/cache/prefetch/stride.hh"
 
+    # Do not consult stride prefetcher on instruction accesses
+    on_inst = False
+
     max_conf = Param.Int(7, "Maximum confidence level")
     thresh_conf = Param.Int(4, "Threshold confidence level")
     min_conf = Param.Int(0, "Minimum confidence level")
@@ -84,6 +127,10 @@ class StridePrefetcher(QueuedPrefetcher):
 
     degree = Param.Int(4, "Number of prefetches to generate")
 
+    # Get replacement policy
+    replacement_policy = Param.BaseReplacementPolicy(RandomRP(),
+        "Replacement policy")
+
 class TaggedPrefetcher(QueuedPrefetcher):
     type = 'TaggedPrefetcher'
     cxx_class = 'TaggedPrefetcher'