-# Copyright (c) 2012, 2014 ARM Limited
+# Copyright (c) 2012, 2014, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
cxx_header = "mem/cache/prefetch/base.hh"
cxx_exports = [
PyBindMethod("addEventProbe"),
+ PyBindMethod("addTLB"),
]
sys = Param.System(Parent.any, "System this prefetcher belongs to")
# Override the normal SimObject::regProbeListeners method and
# register deferred event handlers.
def regProbeListeners(self):
+ for tlb in self._tlbs:
+ self.getCCObject().addTLB(tlb.getCCObject())
for event in self._events:
event.register()
self.getCCObject().regProbeListeners()
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
+ _tlbs = []
+ def registerTLB(self, simObj):
+ if not isinstance(simObj, SimObject):
+ raise TypeError("argument must be a SimObject type")
+ self._tlbs.append(simObj)
+
+class MultiPrefetcher(BasePrefetcher):
+ type = 'MultiPrefetcher'
+ cxx_class = 'MultiPrefetcher'
+ cxx_header = 'mem/cache/prefetch/multi.hh'
+
+ prefetchers = VectorParam.BasePrefetcher([], "Array of prefetchers")
class QueuedPrefetcher(BasePrefetcher):
type = "QueuedPrefetcher"
cxx_header = "mem/cache/prefetch/queued.hh"
latency = Param.Int(1, "Latency for generated prefetches")
queue_size = Param.Int(32, "Maximum number of queued prefetches")
+ max_prefetch_requests_with_pending_translation = Param.Int(32,
+ "Maximum number of queued prefetches that have a missing translation")
queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request")
tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
+ # The throttle_control_percentage controls how many of the candidate
+ # addresses generated by the prefetcher will be finally turned into
+ # prefetch requests
+ # - If set to 100, all candidates can be discarded (one request
+ # will always be allowed to be generated)
+ # - Setting it to 0 will disable the throttle control, so requests are
+ # created for all candidates
+ # - If set to 60, 40% of candidates will generate a request, and the
+ # remaining 60% will be generated depending on the current accuracy
+ throttle_control_percentage = Param.Percent(0, "Percentage of requests \
+ that can be throttled depending on the accuracy of the prefetcher.")
+
class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
cxx_class = 'StridePrefetcher'
pt_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
"Replacement policy of the pattern table")
max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance")
- max_indirect_counter_value = Param.Unsigned(8,
- "Maximum value of the indirect counter")
+ num_indirect_counter_bits = Param.Unsigned(3,
+ "Number of bits of the indirect counter")
ipd_table_entries = Param.MemorySize("4",
"Number of entries of the Indirect Pattern Detector")
ipd_table_assoc = Param.Unsigned(4,
signature_table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
"Replacement policy of the signature table")
- max_counter_value = Param.UInt8(7, "Maximum pattern counter value")
+ num_counter_bits = Param.UInt8(3,
+ "Number of bits of the saturating counters")
pattern_table_entries = Param.MemorySize("4096",
"Number of entries of the pattern table")
pattern_table_assoc = Param.Unsigned(1,
signature_table_assoc = 1
pattern_table_entries = "512"
pattern_table_assoc = 1
- max_counter_value = 15
+ num_counter_bits = 4
prefetch_confidence_threshold = 0.25
lookahead_confidence_threshold = 0.25
cxx_class = "IrregularStreamBufferPrefetcher"
cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
- max_counter_value = Param.Unsigned(3,
- "Maximum value of the confidence counter")
+ num_counter_bits = Param.Unsigned(2,
+ "Number of bits of the confidence counter")
chunk_size = Param.Unsigned(256,
"Maximum number of addresses in a temporal stream")
degree = Param.Unsigned(4, "Number of prefetches to generate")
"Number of entries of the Region Miss Order Buffer")
reconstruction_entries = Param.Unsigned(256,
"Number of reconstruction entries")
+
+class HWPProbeEventRetiredInsts(HWPProbeEvent):
+ def register(self):
+ if self.obj:
+ for name in self.names:
+ self.prefetcher.getCCObject().addEventProbeRetiredInsts(
+ self.obj.getCCObject(), name)
+
+class PIFPrefetcher(QueuedPrefetcher):
+ type = 'PIFPrefetcher'
+ cxx_class = 'PIFPrefetcher'
+ cxx_header = "mem/cache/prefetch/pif.hh"
+ cxx_exports = [
+ PyBindMethod("addEventProbeRetiredInsts"),
+ ]
+
+ prec_spatial_region_bits = Param.Unsigned(2,
+ "Number of preceding addresses in the spatial region")
+ succ_spatial_region_bits = Param.Unsigned(8,
+ "Number of subsequent addresses in the spatial region")
+ compactor_entries = Param.Unsigned(2, "Entries in the temp. compactor")
+ stream_address_buffer_entries = Param.Unsigned(7, "Entries in the SAB")
+ history_buffer_size = Param.Unsigned(16, "Entries in the history buffer")
+
+ index_entries = Param.MemorySize("64",
+ "Number of entries in the index")
+ index_assoc = Param.Unsigned(64,
+ "Associativity of the index")
+ index_indexing_policy = Param.BaseIndexingPolicy(
+ SetAssociative(entry_size = 1, assoc = Parent.index_assoc,
+ size = Parent.index_entries),
+ "Indexing policy of the index")
+ index_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
+ "Replacement policy of the index")
+
+ def listenFromProbeRetiredInstructions(self, simObj):
+ if not isinstance(simObj, SimObject):
+ raise TypeError("argument must be of SimObject type")
+ self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC"))
projects / gem5.git / blobdiff